參數(shù)資料
型號(hào): S29CD016G0JFFM012
廠商: Spansion Inc.
英文描述: 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
中文描述: 32兆位(1米× 32位),16兆位(512k × 32的位),2.5伏,只有突發(fā)模式,雙啟動(dòng),同步讀/寫(xiě)閃存與VersatileI內(nèi)存/輸出
文件頁(yè)數(shù): 28/87頁(yè)
文件大?。?/td> 792K
代理商: S29CD016G0JFFM012
26
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
leaves erroneous data in the address locations being operated on at the time of the RESET# pulse.
These locations require updating after the device resumes standard operations. See
RESET#:
Hardware Reset Pin
on page 26
for further discussion of the RESET# pin and its functions.
RESET#: Hardware Reset Pin
The RESET# pin is an active low signal that is used to reset the device under any circumstances.
A logic
0
on this pin forces the device out of any mode that is currently executing back to the reset
state. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device. To avoid a potential bus contention during a system reset, the device is isolated
from the DQ data bus by tristating the data output pins for the duration of the RESET pulse. All
pins are
don’t cares
during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the
reset operation is internally complete. This action requires between 1 μs and 7μs for either Chip
Erase or Sector Erase. The RY/BY# pin can be used to determine when the reset operation is com-
plete. Otherwise, allow for the maximum reset time of 11 μs. If RESET# is asserted when a
program or erase operation is not executing (RY/BY# =
1
), the reset operation completes within
500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank after
500 ns if the bank was in the read/reset mode at the time RESET# was asserted. If one of the
banks was in the middle of either a program or erase operation when RESET# was asserted, the
user must wait 11 μs before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the ad-
dress locations being operated on at the time of device reset. These locations need updating after
the reset operation is complete. See
Figure 19,
RESET# Timings,
on page 72
for timing
specifications.
Asserting RESET# active during V
CC
and V
IO
power up is required to guarantee proper device ini-
tialization until V
CC
and V
IO
reaches steady state voltages.
Output Disable Mode
See
Table 27 on page 23
Device Bus Operation for OE# Operation in Output Disable Mode.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection ver-
ification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its correspond-
ing programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires V
ID
on address pin A9. Ad-
dress pins A6, A1, and A0 must be as shown in
Table 24 on page 20
(top boot devices) or
Table 25
on page 21
(bottom boot devices). In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order address bits (see
Table 23 on page 19
through
Table 26 on page 22
).
Table 29
shows the remaining address bits that are don’t care.
When all necessary bits are set as required, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via
the command. This method does not require V
ID
. See
Command Definitions
on page 42
for details
on using the autoselect mode.
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