
8
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Asynchronous Read Operation............................................................................................................................................................................27
End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation...........................................................................29
Initial Burst Delay Control.....................................................................................................................................................................................30
Program Operation..................................................................................................................................................................................................45
Erase Operation........................................................................................................................................................................................................48
Data# Polling Algorithm..........................................................................................................................................................................................57
Toggle Bit Algorithm................................................................................................................................................................................................60
Maximum Negative Overshoot Waveform......................................................................................................................................................62
Maximum Positive Overshoot Waveform.........................................................................................................................................................62
I
CC1
Current vs. Time (Showing Active and Automatic Sleep Currents)................................................................................................65
Typical I
CC1
vs. Frequency......................................................................................................................................................................................65
Test Setup....................................................................................................................................................................................................................66
Input Waveforms and Measurement Levels.....................................................................................................................................................66
V
CC
and V
IO
Power-up Diagram..........................................................................................................................................................................67
Conventional Read Operations Timings............................................................................................................................................................68
Burst Mode Read.......................................................................................................................................................................................................70
Asynchronous Command Write Timing............................................................................................................................................................70
Synchronous Command Write/Read Timing.....................................................................................................................................................71
RESET# Timings.........................................................................................................................................................................................................72
WP# Timing................................................................................................................................................................................................................72
Chip/Sector Erase Operation Timings................................................................................................................................................................74
Back-to-Back Cycle Timings..................................................................................................................................................................................74
Data# Polling Timings (During Embedded Algorithms)................................................................................................................................75
Toggle Bit Timings (During Embedded Algorithms).......................................................................................................................................75
DQ2 vs. DQ6 for Erase/Erase Suspend Operations......................................................................................................................................76
Synchronous Data Polling Timing/Toggle Bit Timings....................................................................................................................................76
Sector Protect/Unprotect Timing Diagram......................................................................................................................................................77
Alternate CE# Controlled Write Operation Timings...................................................................................................................................78