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參數(shù)資料
| 型號(hào)： | S29CD016G0JFFM012 |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| 中文描述： | 32兆位（1米× 32位），16兆位（512k × 32的位），2.5伏，只有突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存與VersatileI內(nèi)存/輸出 |
| 文件頁數(shù)： | 32/87頁 |
| 文件大小： | 792K |
| 代理商： | S29CD016G0JFFM012 |
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30
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Burst Access Timing Control
In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial
access delay, delivery of data on the CLK edge, and the length of time data is held.
I nitial Burst Access Delay Control
The device contains options for initial access delay of a burst access. The initial access delay has
no effect on asynchronous read operations.
Burst Initial Access Delay is defined as the number of clock cycles that must elapse from the first
valid clock edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge
when the data is valid.
The burst access is initiated and the address is latched on the first rising CLK edge when ADV#
is active or upon a rising ADV# edge, whichever comes first. (
Table 32
describes the initial access
delay configurations.)
Notes:
1.
2.
3.
4.
5.
Burst access starts with a rising CLK edge and when ADV# is active.
Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
CR [13-10] = 1 or three clock cycles
CR [13-10] = 2 or four clock cycles
CR [13-10] = 3 or five clock cycles
Figure 3. Initial Burst Delay Control
Burst CLK Edge Data Delivery
The device delivers data on the rising of CLK. Bit 6 in the Control Register (CR6) is set to 1, and
is the default configuration.
Burst Data Hold Control
The device is capable of holding data for one CLKs. The default configuration is to hold data for
one CLK and is the only valid state.
Table 32. Burst Initial Access Delay
CR13
CR 12
CR11
CR10
I nitial Burst Access ( CLK cycles)
40 MHz ( 0J ) , 56 MHz ( 0M) , 66 MHz ( 0P) ,
75 MHz ( 0R, 32 Mb only)
0
0
0
0
2
0
0
0
1
3
0
0
1
0
4
0
0
1
1
5
0
1
0
0
6
0
1
0
1
7
0
1
1
0
8
0
1
1
1
9
CLK
ADV#
Addresses
DQ31-DQ0
3
DQ31-DQ0
4
DQ31-DQ0
5
Valid Address
Three CLK Delay
2nd CLK
3rd CLK
4th CLK
5th CLK
1st CLK
Four CLK Delay
Address 1 Latched
Five CLK Delay
D0
D1
D2
D3
D0
D1
D2
D0
D1
D2
D3
D4
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| S29CD016G0JFFM100 | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM102 | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29CD016G0JFFM100 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM102 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM110 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM112 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM200 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
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