參數(shù)資料
型號： S29CD016G0JFFM012
廠商： Spansion Inc.
英文描述： 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
中文描述： 32兆位（1米× 32位），16兆位（512k × 32的位），2.5伏，只有突發(fā)模式，雙啟動，同步讀/寫閃存與VersatileI內(nèi)存/輸出
文件頁數(shù)： 45/87頁
文件大?。?/td> 792K
代理商： S29CD016G0JFFM012
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
43
P r e l i m i n a r y
During the data phase, the first burst data is available after the initial access time delay defined
in the Configuration Register. For subsequent burst data, every rising (or falling) edge of the CLK
triggers the output data with the burst output delay and sequence defined in the Configuration
Register.
Table 41 on page 54
and
Table 42 on page 55
show all the commands executed by the device.
The device automatically powers up in the read/reset state. It is not necessary to issue a read/
reset command after power-up or hardware reset.
Read/Reset Command
After power-up or hardware reset, the device automatically enter the read state. It is not neces-
sary to issue the reset command after power-up or hardware reset. Standard microprocessor
cycles retrieve array data, however, after power-up, only asynchronous accesses are permitted
since the Configuration Register is at its reset state with burst accesses disabled.
The Reset command is executed when the user needs to exit any of the other user command se-
quences (such as autoselect, program, chip erase, etc.) to return to reading array data. There is
no latency between executing the Reset command and reading array data.
The Reset command does not disable the Secured Silicon sector if it is enabled. This function is
only accomplished by issuing the Secured Silicon Sector Exit command.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents.
As such, manufacturer and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to V
ID
. However,
multiplexing high voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect Command operation to supplement traditional PROM program-
ming methodology. The operation is initiated by writing the Autoselect command sequence into
the command register. The bank address (BA) is latched during the autoselect command se-
quence write operation to distinguish which bank the Autoselect command references. Reading
the other bank after the Autoselect command is written results in reading array data from the
other bank and the specified address. Following the command write, a read cycle from address
(BA)XX00h retrieves the manufacturer code of (BA)XX01h. Three sequential read cycles at ad-
dresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh read the three-byte device ID (see
Table 41
).
(The Autoselect Command requires the user to execute the Read/Reset command to return the
device back to reading the array contents.)
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-
ing two unlock write cycles, followed by the program set-up command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The system is
not
required to provide further controls or timings. The device automatically generates the program
pulses and verifies the programmed cell margin.
Table 41 on page 54
and
Table 42 on page 55
show the address and data requirements for the program command sequence.
During the Embedded Program algorithm, the system can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. (See
Write Operation Status
on page 56
for informa-
tion on these status bits.) When the Embedded Program algorithm is complete, the device returns
to reading array data and addresses are no longer latched. Note that an address change is re-
quired to begin read valid array data.
Except for Program Suspend, any commands written to the device during the Embedded Program
Algorithm are ignored. Note that a
hardw are reset
immediately terminates the programming
相關(guān)PDF資料
PDF描述
S29CD016G0JFFM100 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM102 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM110 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM112 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM200 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29CD016G0JFFM100 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM102 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM110 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM112 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD016G0JFFM200 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
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