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參數(shù)資料
| 型號(hào)： | S29CD016G0JFFM012 |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| 中文描述： | 32兆位（1米× 32位），16兆位（512k × 32的位），2.5伏，只有突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存與VersatileI內(nèi)存/輸出 |
| 文件頁數(shù)： | 44/87頁 |
| 文件大小： | 792K |
| 代理商： | S29CD016G0JFFM012 |
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42
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Command Definitions
Writing specific address and data commands or sequences into the command register initiates
device operations.
Table 41 on page 54
and
Table 42 on page 55
define the valid register com-
mand sequences. Writing
incorrect
address and data values
or writing them in the
improper
sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. See
AC Characteristics
on
page 67
for timing diagrams.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embed-
ded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an ad-
dress within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data
with the same exception. See
Sector Erase and Program Suspend Command
on page 47
for more
information on this mode.
The system
must
issue the reset command to re-enable the device for reading array data if DQ5
goes high, or while in the autoselect mode. See
PPB Lock Bit Set Command
on page 51
.
Asynchronous Read Operation (Non-Burst)
on page 27
for more information. See
Sector Erase and
Program Resume Command
on page 49
for more information on this mode.
Reading Array Data in Burst Mode
The device is capable of very fast Burst mode read operations. The configuration register sets the
read configuration, burst order, frequency configuration, and burst length.
Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are
ignored. The device operates like a conventional Flash device. Data is available t
ACC
/t
CE
nanosec-
onds after address becomes stable, CE# become asserted. The device enters the burst mode by
enabling synchronous burst reads in the configuration register. The device exits burst mode by
disabling synchronous burst reads in the configuration register. (See
Command Definitions
on
page 42
). The RESET# command does not terminate the Burst mode. System reset (power on
reset) terminates the Burst mode.
The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output
Enable (OE#) to control normal read and write operations. Moreover, three additional control pins
were added to allow easy interface with minimal glue logic to a wide range of microprocessors /
microcontrollers for high performance Burst read capability. These additional pins are Address
Valid (ADV#) and Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to CLK). The Burst
mode read operation is a synchronous operation tied to the edge of the clock. The microprocessor
/ microcontroller supplies only the initial address, all subsequent addresses are automatically
generated by the device with a timing defined by the Configuration Register definition. The Burst
read cycle consists of an address phase and a corresponding data phase.
During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock
period. Together with the edge of the CLK, the starting burst address is loaded into the internal
Burst Address Counter. The internal Burst Address Counter can be configured to either 2, 4, and
8 double word linear burst, with or without wrap around. S ee
Initial Access Delay
Configuration
on page 33
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29CD016G0JFFM100 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM102 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM110 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM112 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFM200 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
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