參數(shù)資料
型號(hào)： R5F6418JADFE
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 91/128頁
文件大?。?/td> 922K
代理商： R5F6418JADFE
65
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
14.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-
port pin, here generically called Pxn.
Figure 14-2. General Digital I/O(1)
Note:
1.
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD
are common to all ports.
14.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Section 14.4 “Register Description” on page 79, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at
the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output
pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-
up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-
stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is
written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
D
0
1
Q
WRx
RRx
WPx
Pxn
CLR
RESET
Synchronizer
DA
T
A
BUS
PORTxn
Q
L
D
Q
D
Q
PINxn
RESET
RPx
WDx:
WRITE DDRx
WRx:
WPx:
RPx:
RRx:
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
RDx:
WRITE PORTx
READ DDRx
PUD:
PULLUP DISABLE
CLK
I/O:
SLEEP:
I/O CLOCK
SLEEP CONTROL
RDx
CLK
I/O
PUD
WDx
SLEEP
D
Q
CLR
DDxn
Q
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