參數(shù)資料
型號： R5F6418JADFE
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 20/128頁
文件大?。?/td> 922K
代理商： R5F6418JADFE
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
118
16.11.2 TCCR1B – Timer/Counter1 Control Register B
Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the input capture noise canceler. When the noise canceler is activated, the input from the
input capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for
changing its output. The input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled.
Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the input capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is
written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge
will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the input capture register
(ICR1). The event will also set the input capture flag (ICF1), and this can be used to cause an input capture interrupt, if this
interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B
register), the ICP1 is disconnected and consequently the input capture function is disabled.
Bit 5 – Reserved
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when
TCCR1B is written.
Table 16-5. Waveform Generation Mode Bit Description(1)
Mode
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation
TOP
Update of
OCR1x at
TOV1 Flag
Set on
0
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, phase correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, phase correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, phase correct, 10-bit 0x03FF
TOP
BOTTOM
4
0
1
0
CTC
OCR1A
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
BOTTOM
TOP
6
0
1
0
Fast PWM, 9-bit
0x01FF
BOTTOM
TOP
7
0
1
Fast PWM, 10-bit
0x03FF
BOTTOM
TOP
8
1
0
PWM, phase and frequency
correct
ICR1
BOTTOM
9
1
0
1
PWM, phase and frequency
correct
OCR1A
BOTTOM
10
1
0
1
0
PWM, phase correct
ICR1
TOP
BOTTOM
11
1
0
1
PWM, phase correct
OCR1A
TOP
BOTTOM
12
1
0
CTC
ICR1
Immediate
MAX
13
1
0
1
(Reserved)
–
14
1
0
Fast PWM
ICR1
BOTTOM
TOP
15
1
Fast PWM
OCR1A
BOTTOM
TOP
Notes: 1.
The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the func-
tionality and location of these bits are compatible with previous versions of the timer.
Bit
7
6
5
4
3
2
1
0
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value
0
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