參數(shù)資料
型號(hào)： R5F6418JADFE
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 24/128頁
文件大?。?/td> 922K
代理商： R5F6418JADFE
121
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit 7, 6 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
input capture interrupt is enabled. The corresponding interrupt vector (See Section 12. “Interrupts” on page 50) is executed
when the ICF1 flag, located in TIFR1, is set.
Bit 4, 3 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
output compare B match interrupt is enabled. The corresponding interrupt vector (See Section 12. “Interrupts” on page 50) is
executed when the OCF1B flag, located in TIFR1, is set.
Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
output compare A match interrupt is enabled. The corresponding interrupt vector (See Section 12. “Interrupts” on page 50) is
executed when the OCF1A flag, located in TIFR1, is set.
Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
overflow interrupt is enabled. The corresponding interrupt vector (See Section 12. “Interrupts” on page 50) is executed when
the TOV1 flag, located in TIFR1, is set.
16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit 7, 6 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the input capture register (ICR1) is set by the WGM13:0
to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the input capture interrupt vector is executed. Alternatively, ICF1 can be cleared by
writing a logic one to its bit location.
Bit 4, 3 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit
7
6
5
4
32
10
–
ICIE1
–
OCIE1B
OCIE1A
TOIE1
TIMSK1
Read/Write
R
R/W
R
R/W
Initial Value
0
Bit
765
43210
––
ICF1
––
OCF1B
OCF1A
TOV1
TIFR1
Read/Write
R
R/W
R
R/W
Initial Value
000
00000
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