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參數(shù)資料
| 型號： | R5F6418JADFE |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 19/128頁 |
| 文件大?。?/td> | 922K |
| 代理商： | R5F6418JADFE |
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117
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Table 16-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and
frequency correct, PWM mode.
Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 16-5. Modes of
operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and
three types of pulse width modulation (PWM) modes. See (Section 16.9 “Modes of Operation” on page 108).
Table 16-3. Compare Output Mode, Fast PWM(1)
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 14 or 15: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on compare match, set OC1A/OC1B at
BOTTOM (non-inverting mode)
1
Set OC1A/OC1B on compare match, clear OC1A/OC1B at
BOTTOM (inverting mode)
Note:
1.
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the com-
pare match is ignored, but the set or clear is done at BOTTOM. See
Section 16.9.3 “Fast PWM Mode” on page 110 for more details.
Table 16-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 9 or 11: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on compare match when up-counting. Set
OC1A/OC1B on compare match when downcounting.
1
Set OC1A/OC1B on compare match when up-counting. Clear
OC1A/OC1B on compare match when downcounting.
Note:
1.
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
Section 16.9.4 “Phase Correct PWM Mode” on page 111 for more details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F6418JANFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE_12 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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