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參數(shù)資料
| 型號(hào)： | R5F6418JADFE |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 31/128頁(yè) |
| 文件大?。?/td> | 922K |
| 代理商： | R5F6418JADFE |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
128
18.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR2A and OCR2B). Whenever
TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the output compare flag (OCF2A or
OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output
compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the output
compare flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the
match signal to generate an output according to operating mode set by the WGM22:0 bits and compare output mode
(COM2x1:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the
extreme values in some modes of operation (Section 18.7 “Modes of Operation” on page 130).
Figure 18-3 shows a block diagram of the output compare unit.
Figure 18-3. Output Compare Unit, Block Diagram
The OCR2x register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and
clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR2x compare register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR2x buffer register, and if double buffering is disabled the CPU will access the OCR2x directly.
18.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force
output compare (FOC2x) bit. Forcing compare match will not set the OCF2x flag or reload/clear the timer, but the OC2x pin
will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set,
cleared or toggled).
18.5.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an
interrupt when the Timer/Counter clock is enabled.
OCFnx (Int. Req.)
= (8-bit Comparator)
OCRnx
Waveform Generator
TCNTn
OCnx
top
bottom
FOCn
WGMn1:0
COMnX1:0
DATA BUS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F6418JANFD | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE_12 | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFD | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFE | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:RENESAS MCU |
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