參數(shù)資料
型號: R5F6418JADFE
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù): 17/128頁
文件大?。?/td> 922K
代理商: R5F6418JADFE
115
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Figure 16-11 shows the same timing data, but with the prescaler enabled.
Figure 16-11.Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM
mode the OCR1x register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by
BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM.
Figure 16-12.Timer/Counter Timing Diagram, no Prescaling
OCRnx - 1
clkI/O
(clkI/O/8)
TCNTn
OCRnx
OCFnx
clkTn
OCRnx
OCRnx + 1
OCRnx Value
OCRnx + 2
TOP - 1
clkI/O
(clkI/O/1)
TCNTn
(CTC and FPWM)
OCRnx
(Update at TOP)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn
(if used as TOP)
clkTn
TOP
Old OCRnx Value
New OCRnx Value
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP -1
TOP -2
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