參數(shù)資料
型號： R5F6418JADFE
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 58/128頁
文件大小： 922K
代理商： R5F6418JADFE
35
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
10.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides
various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
When enabled, the brown-out detector (BOD) actively monitors the power supply voltage during the sleep periods. To further
save power, it is possible to disable the BOD in some sleep modes. See Section 10.2 “BOD Disable(1)” on page 36 for more
details.
10.1
Sleep Modes
Figure 9-1 on page 24 presents the different clock systems in the Atmel ATmega48PA/88PA/168PA, and their distribution.
The figure is helpful in selecting an appropriate sleep mode. Table 10-1 shows the different sleep modes, their wake up
sources BOD disable ability(1).
Note:
1.
BOD disable is only available for ATmega48PA/88PA/168PA.
To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM2, SM1, and SM0 bits in the SMCR register select which sleep mode (idle, ADC noise reduction, power-
down, power-save, standby, or extended standby) will be activated by the SLEEP instruction. See Table 10-2 on page 39 for
a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles
in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during
sleep mode, the MCU wakes up and executes from the reset vector.
Table 10-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sof
tware
B
O
D
Disable
Sleep Mode
cl
k
CP
U
cl
k
FLA
SH
cl
k
IO
cl
k
AD
C
cl
k
AS
Y
Main
Clo
ck
Source
Enabled
T
imer
Oscill
at
or
Enabled
INT1,
INT0
an
d
Pin
Change
TW
IAd
dre
s
Match
Ti
m
er
2
SPM/EEP
ROM
R
ead
y
AD
C
WDT
Oth
e
rI
/O
Idle
X
X(2)
X
ADC Noise
Reduction
X
X(2)
X(3)
X
X(2)
X
Power-down
X(3)
X
Power-save
X
X(2)
X(3)
X
Standby(1)
X
X(3)
X
Extended
Standby
X(2)
X
X(2)
X(3)
X
Note:
1.
Only recommended with external crystal or resonator selected as clock source.
2.
If Timer/Counter2 is running in asynchronous mode.
3.
For INT1 and INT0, only level interrupt.
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