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參數(shù)資料
| 型號(hào)： | R5F6418JADFE |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 2/128頁(yè) |
| 文件大?。?/td> | 922K |
| 代理商： | R5F6418JADFE |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
100
16.3
Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The
16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for
temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers
within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit
register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the
16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve
using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the
high byte.
The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the
temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 registers. Note that when
using “C”, the compiler handles the 16-bit access.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two
instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or
any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when
both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during
the 16-bit access.
Assembly Code Examples(1)
...
; Set TCNT
1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT
1H,r17
out
TCNT
1L,r16
; Read TCNT
1 into r17:r16
in
r16,TCNT
1L
in
r17,TCNT
1H
...
C Code Examples(1)
unsigned int
i;
...
/* Set TCNT
1 to 0x01FF */
TCNT
1 = 0x1FF;
/* Read TCNT
1 into i */
i = TCNT
1;
...
Note:
1.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined
with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F6418JANFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE_12 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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