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參數(shù)資料
| 型號(hào)： | R5F6418JADFE |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 47/128頁(yè) |
| 文件大?。?/td> | 922K |
| 代理商： | R5F6418JADFE |
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25
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
9.1.3
Flash Clock – clkFLASH
The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock.
9.1.4
Asynchronous Timer Clock – clkASY
The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an
external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when
the device is in sleep mode.
9.1.5
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.
9.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the
selected source is input to the AVR clock generator, and routed to the appropriate modules.
9.2.1
Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz
system clock. The startup time is set to maximum and time-out period enabled.
(CKSEL = “0010”, SUT = “10”, CKDIV8 = “0”). The default setting ensures that all users can make their desired clock source
setting using any available programming interface.
9.2.2
Clock Startup Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be
considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by
all other reset sources. Section 11. “System Control and Reset” on page 41 describes the start conditions for the internal
reset. The delay (tTOUT) is timed from the watchdog oscillator and the number of cycles in the delay is set by the SUTx and
CKSELx fuse bits. The selectable delays are shown in Table 9-2. The frequency of the watchdog oscillator is voltage
dependent as shown in Section 30. “Typical Characteristics” on page 279.
Table 9-1.
Device Clocking Options Select(1)
Device Clocking Option
CKSEL3...0
Low Power Crystal Oscillator
1111 - 1000
Full Swing Crystal Oscillator
0111 - 0110
Low Frequency Crystal Oscillator
0101 - 0100
Internal 128kHz RC Oscillator
0011
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0001
Note:
1.
For all fuses “1” means unprogrammed while “0” means programmed.
Table 9-2.
Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V)
Typ Time-out (VCC = 3.0V)
Number of Cycles
0ms
0
4.1ms
4.3ms
512
65ms
69ms
8K (8,192)
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相關(guān)代理商/技術(shù)參數(shù) |
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| R5F6418JANFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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| R5F6418JAPFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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