參數(shù)資料
型號(hào): R5F6418JADFE
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù): 30/128頁
文件大?。?/td> 922K
代理商: R5F6418JADFE
127
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
18.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a block diagram
of the counter and its surrounding environment.
Figure 18-2. Counter Unit Block Diagram
Signal description (internal signals):
count
Increment or decrement TCNT2 by 1.
direction
Selects between increment and decrement.
clear
Clear TCNT2 (set all bits to zero).
clkTn
Timer/Counter clock, referred to as clkT2 in the following.
top
Signalizes that TCNT2 has reached maximum value.
bottom
Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2).
clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock
source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter control
register (TCCR2A) and the WGM22 located in the Timer/Counter control register B (TCCR2B). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC2A and
OC2B. For more details about advanced counting sequences and waveform generation, see
The Timer/Counter overflow flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can
be used for generating a CPU interrupt.
top
bottom
TOVn
(Int. Req.)
DATA BUS
Control Logic
TCNTn
clkTn
clear
count
direction
clkI/O
Prescaler
T/C
Oscillator
TOSC1
TOSC2
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