參數(shù)資料
型號(hào)： R5F6418JADFE
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 11/128頁
文件大?。?/td> 922K
代理商： R5F6418JADFE
109
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
16.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register are used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A
(WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNT1) increases until a compare match
occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 16-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag
according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used
for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none
or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new
value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The
counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare
match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare
match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the
port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a
maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the
following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to
0x0000.
12
TCNTn
(COMnA1:0 = 1)
OCnA
(Toggle)
Period
3
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
4
fOCnA
fclk_I/O
2N
×
1 OCRnA
+
()
×
-----------------------------------------------------
=
相關(guān)PDF資料
PDF描述
R5F64200LFB 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
R5F64200JFB 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
R5F64201JFB 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
R5F64201KFB 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
R5F6420FLFB 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F6418JANFD 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F6418JANFE 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F6418JANFE_12 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F6418JAPFD 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F6418JAPFE 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*