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參數(shù)資料
| 型號： | R5F6418JADFE |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 84/128頁 |
| 文件大?。?/td> | 922K |
| 代理商： | R5F6418JADFE |
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59
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
13.
External Interrupts
The external interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if enabled, the
interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as outputs. This feature provides a way of
generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin toggles. The pin
change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles. The pin change interrupt PCI0 will trigger if any
enabled PCINT[7:0] pin toggles. The PCMSK2, PCMSK1 and PCMSK0 registers control which pins contribute to the pin
change interrupts. Pin change interrupts on PCINT23...0 are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the
specification for the external interrupt control register A – EICRA. When the INT0 or INT1 interrupts are enabled and are
configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
Section 9.1 “Clock Systems and their Distribution” on page 24. Low level interrupt on INT0 and INT1 is detected
asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode.
The I/O clock is halted in all sleep modes except Idle mode.
Note:
Note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before
the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The start-up time is
defined by the SUT and CKSEL fuses as described in
13.1
Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 13-1.
Figure 13-1. Timing of Pin Change Interrupts
clk
pin_lat
pin_sync
PCINT(0)
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
pin_lat
pin_sync
pcint_sync
clk
x
0
clk
pcint_setflag
PCINT(0) in PCMSK(x)
PCINT(0)
PCIF
pcint_in_(0)
DQ
LE
DQ
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F6418JANFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JANFE_12 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFD | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6418JAPFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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