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| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 96/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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96
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
BR0#
BR1#
I/O
I
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
BSEL[1:0]
I/O
These signals are used to select the system bus frequency. A BSEL[1:0] = “01” will
select a 100 MHz system bus and a BSEL[1:0] = “11” will select a 133 MHz system
bus frequency. The frequency is determined by the processor(s), chipset, and
frequency synthesizer capabilities. All system bus agents must operate at the same
frequency. The Pentium III processor operates at 100 MHz and 133 MHz system
bus frequencies. Individual processors will only operate at their specified system
bus frequency. Either 100 MHz or 133 MHz, not both.
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 MHz system bus frequency.
These signals must be pulled up to 3.3V with 1K
resistors and provided as
frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operating at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See
Section 2.8.2
for
implementation details.
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEP[7:0]#
I/O
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
Table 41. Signal Description
(Sheet 3 of 7)
Name
Type
Description
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate bu
signal protocol, as shown below.
BR[1:0]# Signal Agent IDs
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
Pin Sampled Active in RESET#
Agent ID
BR0#
0
BR1#
1
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