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參數資料
| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數： | 15/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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Datasheet
15
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the
Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide
(Order Number 243192).
Due to the inability of processors to recognize bus transactions during the Sleep and Deep Sleep
states, 2-way MP systems are not allowed to have one processor in Sleep/Deep Sleep state and the
other processor in Normal or Stop-Grant state simultaneously.
2.2.1
Normal State—State 1
This is the normal operating state for the processor.
2.2.2
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the
Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide
(Order Number 243192) for more information.
FLUSH# will be serviced during the AutoHALT state, and the processor will return to the
AutoHALT state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
2.2.3
Stop-Grant State—State 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to V
TT
) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# and FLUSH# will not be serviced during Stop-Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see
Section 2.2.4
). A transition to the Sleep state (see
Section 2.2.5
) will occur with the
assertion of the SLP# signal.
While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only
serviced when the processor returns to the Normal state. Only one occurrence of each event will be
recognized and serviced upon return to the Normal state.
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