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參數(shù)資料
| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 39/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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Datasheet
39
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
3.0
Signal Quality Specifications
Signals driven on the Pentium
III
processor system bus should meet signal quality specifications to
ensure that the components read data properly and to ensure that incoming signals do not affect the
long term reliability of the component. Specifications are provided for simulation and
measurement at the processor core; they should not be tested at the edge fingers.
The AGTL+ and non-AGTL+ signal quality specifications listed in this section apply to
Pentium
III
processors with CPUID=068xh. It is recommended that these specifications be used
with Pentium
III
processors with CPUID=067xh, however any deviations from these guidelines
must be verified with the specifications listed in the
Pentium
II Processor Developer's Manual
(Order Number 243502).
3.1
BCLK, PICCLK, and PWRGOOD Signal Quality
Specifications and Measurement Guidelines
Table 19
describes the signal quality specifications at the processor core for the Pentium
III
processor system bus clock (BCLK), APIC clock (PICCLK), and PWRGOOD signals.
Figure 14
describes the signal quality waveform for the system bus clock at the processor core pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
III processor frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
specification is an absolute value.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the PICCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
specification is an absolute value.
Table 19. BCLK, PICCLK, and PWRGOOD Signal Quality Specifications at the
Processor Core
1
V# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: V
IN
Absolute Voltage Range
V2: Rising Edge Ringback
–0.7
3.3
V
14
2.0
V
14
2
V3: Falling Edge Ringback
0.5
0.7
V
V
14
14
2
3
Figure 14. BCLK and PICCLK Generic Clock Waveform
V2
V1
V3
V3
T6/T26
T5/T25
T4/T24
V4
V5
T3/T23
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