參數(shù)資料
型號(hào)： pentium III CPU
廠商： Intel Corp.
英文描述： Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器)
中文描述： 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242）
文件頁(yè)數(shù)： 32/102頁(yè)
文件大?。?/td> 920K
代理商： PENTIUM III CPU
32
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins
1, 2, 3
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. Valid delay timings for these signals are specified into 25
to 1.5 V and with VREF at 1.0 V.
5. Valid delay timings for these signals are specified into 50
to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchronous.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.This should be measured after V
CCCORE
, V
CCL2
/V
CC3.3
, and BCLK become stable.
11.This specification applies to the Pentium
III processor with a system bus frequency of 100 MHz
.
12.This specification applies to the Pentium
III processor with a system bus frequency of 133 MHz
.
Table 13. Valid System Bus, Core Frequency, and Cache Bus Frequencies
1
Processor
Core Frequency (MHz)
BCLK Frequency (MHz)
Frequency Multiplier
L2 Cache (MHz)
450
500
533B
533EB
550
550E
600
600B
600E
600EB
650
667
700
733
750
800
800EB
850
866
933
1.0B GHz
450
500
533
533
550
550
600
600
600
600
650
666.67
700
733
750
800
800
850
866
933
1000.0
100
100
133
133
100
100
100
133
100
133
100
133
100
133
100
100
133
100
133
133
133
9/2
5
4
4
11/2
11/2
6
9/2
6
9/2
13/2
5
7
11/2
15/2
8
6
17/2
13/2
7
15/2
225
250
267
533
275
550
300
300
600
600
650
666.67
700
733
750
800
800
850
866
933
1000.0
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
-0.20
-0.14
-0.10
1.90
1.20
1.20
0.85
0.58
0.80
1.00
3.15
2.20
2.70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
8
8
8
9
9
9
9
9
9
11
4, 10, 13
5, 11, 13
5, 11, 12, 14
6, 7, 8, 11, 13
6, 7, 8, 12, 13
6, 7, 8, 11, 12, 14
9, 11, 13
9, 12, 13
9, 11, 12, 14
7, 10
T8: AGTL+ Input Setup Time
T9: AGTL+ Input Hold Time
T10: RESET# Pulse Width
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