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參數(shù)資料
| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 16/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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16
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
2.2.4
HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the Pentium
III
processor system bus while in
Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the
Pentium
III
processor system bus has been serviced (whether by the processor or another agent on
the Pentium
III
processor system bus). After the snoop is serviced, the processor will return to the
Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5
Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or
AutoHALT states.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see
Section 2.2.6
). Once in the Sleep or Deep Sleep states, the
SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is
stopped. It is recommended that the BCLK input be held low during the Deep Sleep State.
Stopping of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
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