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參數資料
| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數： | 18/102頁 |
| 文件大小： | 920K |
| 代理商： | PENTIUM III CPU |
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18
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
2.4.1
Processor V
CC
CORE
Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep an interconnect resistance from the regulator (or VRM pins) to the SC242 connector of
less than 0.3 m
. This can be accomplished by keeping a maximum distance of 1.0 inches between
the regulator output and SC242 connector. The recommended V
CCCORE
interconnect is a 2.0 inch
wide by 1.0 inch long (maximum distance between the SC242 connector and the VRM connector)
plane segment with a 1-ounce plating. Bulk decoupling for the large current swings when the part
is powering on, or entering/exiting low power states, is provided on the voltage regulation module
(VRM). If using Intel’s enabled VRM solutions see developer.intel.com for the specification and a
list of qualified vendors. The V
CCCORE
input should be capable of delivering a recommended
minimum dIcc
CORE
/dt (defined in
Table 8
) while maintaining the required tolerances (also defined
in
Table 8
).
2.4.2
Processor System Bus AGTL+ Decoupling
The Pentium
III
processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system baseboard for proper AGTL+ bus
operation. See AP-906,
100 MHz AGTL+ Layout Guidelines for the Pentium
III
Processor and
Intel
440BX AGPset
(Order Number 245086) or the appropriate platform design guide, AP-907,
Pentium
III
Processor Power Distribution Guidelines
(Order Number 245085), and the GTL+
buffer specification in the
Pentium
II Processor Developer's Manual
(Order Number 243502) for
more information.
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the Pentium
III
processor system bus
interface. All Pentium
III
processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the
P6 Family of Processors Hardware Developer's Manual
(Order Number 244001) for further details.
2.6
Voltage Identification
There are five voltage identification pins on the SC242 connector. These pins can be used to
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to V
SS
on the processor. The combination of opens and shorts defines
the voltage required by the processor core. The VID pins are needed to cleanly support voltage
specification variations on current and future Pentium
III
processors. VID[4:0] are defined in
Table 3
. A ‘1’ in this table refers to an open pin and a ‘0’ refers to a short to ground. The power
supply must supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future Pentium
III
processors, the range of values in
bold
in
Table 3
should be supported. A smaller range will risk the ability of the system to migrate
to a higher performance Pentium
III
processor and/or maintain compatibility with current
Pentium
III
processors.
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