參數(shù)資料
型號(hào)： pentium III CPU
廠商： Intel Corp.
英文描述： Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器)
中文描述： 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242）
文件頁(yè)數(shù)： 30/102頁(yè)
文件大?。?/td> 920K
代理商： PENTIUM III CPU
30
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to V
TT
at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the V
TT
voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called V
REF
.
Table 11
lists the nominal specification for the AGTL+ termination voltage (V
TT
). The AGTL+
reference voltage (V
REF
) is generated on the processor substrate for the processor core, but should
be set to 2/3 V
TT
for other AGTL+ logic using a voltage divider on the baseboard. It is important
that the baseboard impedance be specified and held to a ±15% tolerance, and that the intrinsic trace
capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on
the GTL+ buffer specification, see the
Pentium
II Processor Developer's Manual
(Order Number
243502) and AP-585,
Pentium
II Processor GTL+ Guidelines
(Order Number 243330).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
III processor frequencies.
2. Pentium III processors contain AGTL+ termination resistors at the end of each signal trace on the processor
substrate. Pentium III processors generate V
REF
on the processor substrate by using a voltage divider on
V
TT
supplied through the SC 242 connector.
3. V
TT
must be held to 1.5 V ±9%; dI
CCVTT
/dt is specified in
Table 8
. It is recommended that V
TT
be held to
1.5 V ±3% while the Pentium III processor system bus is idle. This is measured at the processor edge
fingers.
4. R
TT
must be held within a tolerance of ±5%
5. V
REF
is generated on the processor substrate to be 2/3 V
TT
±2% nominally.
2.13
System Bus AC Specifications
The Pentium
III
processor system bus timings specified in this section are defined at the Pentium
III
processor core pads. Unless otherwise specified, timings are tested at the processor core during
manufacturing. See
Section 7.0
for the Pentium
III
processor edge connector signal definitions. See
Section 5.6
for the Pentium
III
processor closest accessible core pad to substrate via assignment.
Table 12
through
Table 18
list the AC specifications associated with the Pentium
III
processor
system bus. These specifications are broken into the following categories:
Table 12
through
Table 13
contain the system bus clock core frequency and cache bus frequencies,
Table 14
contains
the AGTL+ specifications,
Table 15
contains the CMOS signal group specifications,
Table 16
contains timings for the Reset conditions,
Table 17
covers APIC bus timing, and
Table 18
covers
TAP timing.
All Pentium II processor system bus AC specifications for the AGTL+ signal group are relative to
the rising edge of the BCLK input. All AGTL+ timings are referenced to V
REF
for both ‘0’ and ‘1’
logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium
III
processor in Viewlogic XTK model format (formerly known as QUAD format) as
Table 11. AGTL+ Bus Specifications
1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
TT
R
TT
V
REF
Bus Termination Voltage
Termination Resistor
Bus Reference Voltage
1.365
1.50
56
2/3 V
TT
1.635
V
V
3
4
5
0.95
1.05
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