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參數(shù)資料
| 型號： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁數(shù)： | 92/193頁 |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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Data Sheet
181
Rev. 1.0, 2005-06-02
OctalLIU
TM
PEF 22508 E
Operational Description
7
Operational Description
7.1
Operational Overview
Every of the eight channels of the OctalLIU
TM can be operated in two clock modes, which are either E1 mode or
T1/J1 mode, selected by the register bit GCM2.VFREQ_EN, see Chapter 3.5.5:
In the so called “flexible master clocking mode” (GCM2.VFREQ_EN = 1) all eight ports can work in E1 or in
T1 mode individually, independent from another.
In the so called “clocking fixed mode” (GCM2.VFREQ_EN = 0) all eight ports must work together either in E1
or in T1 mode.
The device is programmable via one of the three integrated micro controller interfaces which are selected by
strapping of the pins IM(1:0):
The asynchronous interface has two modes: Intel (IM(1:0) = 00
b) and Motorola (IM(1:0) = 01b). This
interface enables byte or word access to all control and status registers, see Chapter 3.5.1.
SPI interface (IM(1:0) = 10
b), see Chapter 3.5.2.2.
SCI interface (IM(1:0) = 11
b), see Chapter 3.5.2.1.
The OctalLIU
TM has three different kinds of registers:
The control registers configure the whole device and have write and read access.
The status registers are read-only and are updated continuously. Normally, the processor reads the status
registers periodically to analyze the alarm status and signaling data.
The interrupt status registers are read-only and are cleared by reading (“rsc”). They are updated (set)
continuously. Normally, the processor reads the interrupt status registers after an interrupt occurs at pin INT.
Masking can be done with the appropriate interrupt mask registers. Mask registers are control registers.
All this registers can be separate into two groups:
Global registers are not belonging especially to one of the eight channels. The higher address byte is 00
H.
The other registers are belonging to one of the eight channels. The higher address bytes - marked as xx
H in
the register description - are identical to the numbers 0 up to 7 of the appropriate channels. So every of this
registers exist eight time in the whole device.
7.2
Device Reset
After the device is powered up, the OctalLIU
TM must be forced to the reset state first.
The OctalLIU
TM is forced to the reset state if a low signal is input on pin RES for a minimum period of 10
s, see
Figure 42. During reset the OctalLIU
TM
Needs an active clock on pin MCLK
The pin COMP must be 0.
The pins IM(1:0) must have defined values to select the micro controller interface.
Only if IM(1:0) = 11
b (SCI interface is selected) the pins A(5:0) must have defined values to select the SCI
source address of the device.
Only if IM1 = 1 (SCI or SPI interface is selected) the pins D(15:5) must have defined values to configure the
central PLL in the master clocking unit of the device.
During and after reset all internal flip-flops are reset and most of the control registers are initialized with default
values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is powered up.
After reset the complete device is initialized, especially to E1 operation and “flexible master clocking mode”. The
complete initialization is listed in Table 68. Additionally all interrupt mask registers IMR1, IMR3, IMR4, IMR6 and
IMR7 are initialized to FF
H, so that not masking is performed.
After reset the OctalLIU
TM must be configured first. General guidelines for configuration are described in
Chapter 7.4 for E1 mode and Chapter 7.5 for T1/J1 mode.
For reset see also Chapter 3.5.5.1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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