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參數(shù)資料
| 型號(hào)： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁(yè)數(shù)： | 93/193頁(yè) |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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OctalLIU
TM
PEF 22508 E
Operational Description
Data Sheet
182
Rev. 1.0, 2005-06-02
7.3
Device Initialization
After reset, the OctalLIU
TM is initialized for E1 with register values listed in the following table.
7.4
Device Configuration in E1 Mode
E1 Configuration
For a correct start up of the primary access interface a set of parameters specific to the system and hardware
environment must be programmed after reset goes inactive. Both the basic and the operational parameters must
be programmed before the activation procedure of the PCM line starts. Such procedures are specified in ITU-T
and ETSI recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily
makes sense when basic operation via the PCM line is guaranteed. Table 69 gives an overview of the most
important parameters in terms of signals and control bits which are to be programmed in one of the above steps.
The sequence is recommended but not mandatory. Accordingly, parameters for the basic and operational set up,
for example, can be programmed simultaneously. The bit MR1.PMOD should always be kept low (otherwise T1/J1
mode is selected).
Table 68
Initial Values after Reset
Register
Reset Value
Meaning
LIM0, LIM1,
PCD, PCR
00
H, 00H,
00
H, 00H
Slave Mode, local loop off
Analog interface selected; remote loop off; Pulse count for LOS detection
cleared; Pulse count for LOS recovery cleared
XPM(2:0)
40
H, 03H, 7BH E1 Transmit pulse template for 0 m but with unreduced amplitude (note that
transmitter is in tristate mode)
IMR(7:0)
FF
H
All interrupts are disabled
GCR
00
H
Internal second timer, power on
CMR1
00
H
RCLK output: DPLL clock, DCO-X enabled, DCO-X internal reference clock
CMR2
00
H
RCLK selected, XCLK selected
PC(3:1)
00
H, F0H
00
H, 00H
Functions of ports RP(A to B) are reserved, function of port RPC is RCLK
output (but is only pulled up, because PC5.CRP = 0 after reset), functions
of ports XP(A to B) are reserved.
PC5
00
H
FCLKR, FCLKX, RCLK configured to inputs,
GCM(6:1)
GCM2 = 10
H,
others 00
H
“Flexible master clocking mode” selected
GPC(5:3)
65
H, 43H, 21H
Source for RCLK1 up to RCLK7 are the appropriate channels (only valid for
COMP = 0)
GPC6
07
H
QuadLIU compatible system interface multiplexed modes are selected,
source for RCLK8 is channel 8 (both only valid for COMP = 0)
CMR(6:4)
00
H
Recovered line clock drives RCLK
GPC2
00
H
Source for SEC and RCLK1 is channel 1
TXP(16:1)
TXP(1:8) = 38
H
TXP(9:16) = 00
H
This registers are not used after reset because XPM2.XPDIS = 0
INBLDTR
00
H
Minimum In-band loop detection time
ALS
00
H
No automatic loop switching is performed
PRBSTS(4:1)
all 00
H
No time slots are selected for PRBS pattern
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
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