
OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
80
Rev. 1.0, 2005-06-02
example once per second, using the ISR3.SEC interrupt. In case PRBSSTA.PRS(2:1) is unequal 11
B, the
interrupt mask bits should be cleared to return to normal operation.
Because every bit error in the PRBS sequence increments the bit error counter BEC, no special status information
like “PRBS detected with errors” is given here.
3.11.2
In-Band Loop Generation, Detection and Loop Switching
Detection and generation of In-band Loop code is supported by the OctalLIU
TM on the line side and on the framer
side independent from another.
The OctalLIU
TM generates and detects unframed In-band codes where the complete data stream is used by the
In-band signaling information.The so called loop-up code (for loop activation) and loop-down code (for loop
deactivation) are recognized.
The maximum allowed bit error rate within the loop codes can be up to 10
-2 for proper detection of the loop codes.
One “In-band loop sequence” consists of a bit sequence of 51200 consecutive bits. The In-band loop code
detection is based on the examination of such “In-band loop sequences”.
The following In-band loop code functionality is performed by the OctalLIU
TM:
The necessary reception time of In-band loop codes until an automatic loop switching is performed is
configured for the system side by the register bits INBLDTR.INBLDT(1:0) (INBLDTR). Configuring for the line
side is done by INBLDTR.INBLDR(1:0). If for example INBLDTR.INBLDR(1:0) = 00
B a time of 16 “In-band
loop sequences” (16 x 51200 bits) is selected for the line side.
The interrupt status register bits ISR6.(3:0) reflects the type of detected In-band loop code. Masking can be
done by IMR6(3:0). The status bits are set after one “In-band loop sequence” is detected (no dependency on
INBLDTR).
Transmission of In-Band loop codes is enabled by programming MR3.XLD/XLU in E1 mode or MR5.XLD/XLU
in T1/J1 mode. Transmission of codes is done by the OctalLIU
TM lasting for at least 5 seconds.
The OctalLIU
TM also offers the ability to generate and detect flexible In-band loop-up and loop-down patterns
(LCR1.LLBP = 1) (LCR1). Programming of these patterns is done in registers LCR2 and LCR3 (LCR2). The
pattern length is individually programmable in length from 2 to 8 bits by LCR1.LAC(1:0) and LCR1.LDC(1:0).
A shorter pattern can be inplemented by configuring a repeating pattern in the LCR2 and LCR3.
Automatic loop switching (activation and deactivation, for remote loop, see Chapter 3.11.3 and local loop, see
Chapter 3.11.4) based on In-band Loop codes can be done. Two kinds of line loop back (LLB) codes are
defined in ANSI-T1.403, 1999 in chapter 9.4.1.1 and 9.4.1.2. respectively. Automatic loop switching must be
enabled through configuration register bits ALS.SILS for the In-Band Loop codes coming from the system side
and ALS.LILS for the In-Band Loop codes coming from the line side respectively. Masking of ISR6.(3:0) for
interrupt can be done by register bits IMR6.(3:0). The interrupt status register bits ISR6.(3:0) (ISR6) will be set
to 1 if an appropriate In-Band code were detected, independent if automatic loop switching is enabled.
(Because the controller knows if automatic loop switching is enabled, it knows if a loop is activated or not.)
Code detection status only for the line side is displayed in E1 mode in status register bits LSR2.LLBDD /
LLBAD and in T1/J1 mode in LSR1.LLBDD / LLBAD.
Only unframed In-Band loop code can be generated and detected.
Automatic loop switching is logically ORd with the appropriate loop switching by register bits.
Table 28
Supported PRBS Polynomials
TPC0.PRP(1:0)
TPC0.PRM
LCR1.LLBP
Kind of Polynomial Comment
00
01 or 11
X
2
11 -1
01
01 or 11
X
2
15 -1
10
01 or 11
X
2
20 -1
11
01 or 11
X
2
23 -1
XX
00
0
2
15 -1
SW compatible to
QuadLIU
XX
00
1
2
20 -1