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參數(shù)資料
| 型號(hào)： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁(yè)數(shù)： | 166/193頁(yè) |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
74
Rev. 1.0, 2005-06-02
Figure 31
Clocking and Data in Remote Loop Configuration
3.9.5
Dual Transmit Elastic Buffer
The received single rail bit stream from pin XDI or dual rail bit stream from the pins XDIP and XDIN are optionally
stored in the transmit elastic buffer, see Figure 29. The tansmit elastic buffer is organized as the receive elastic
buffer. The functions are also equal to the receive side. Programming of the dual transmit buffer size is done by
DIC1.XBS(1:0) in the same way as programming of the dual receive buffer size by DIC1.RBS(1:0), see Table 21:
The functions of the transmit buffer are:
Clock adoption between framer transmit clock (FCLKX) and internally generated transmit route clock, see
Compensation of input wander and jitter.
Reporting and controlling of slips
Writing of received data from XDIP/XDIN is controlled by the internal transmit clock. Selection of FCLKX or FCLKR
is possible, see multiplexer “E” in Figure 29. (If the DCO-R output is selected, the DCO_R output is also output at
FCLKR.)
Reading of stored data is controlled by the clock generated either by the DCO-X circuitry or the externally
generated TCLK. With the de-jittered clock data is read from the dual transmit elastic buffer and are forwarded to
the transmitter. Reporting and controlling of slips is done according to the receive direction. Positive/negative slips
are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is bypassed data is directly
transferred to the transmitter.
3.9.6
Programmable Pulse Shaper and Line Build-Out
The transmitter includes a programmable pulse shaper to generate transmit pulse masks according to:
For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for different cable lengths), see
load = 100
For E1: ITU-T G703 11/2001, figure 15 (for 0 m cable length) see Figure 55; ITU-T G703 11/2001, figure 20
(for DCIM mode), see Figure 32 for measurement configuration were R
load = 120 or Rload = 75
The transmit pulse shape (U
PULSE) is programmed either
Pulse
Shaper,
LBO
Encoder
XDATA
XCLK
XL2
DCO-X
MCLK
OctalLIU_remote_loop_clocking
Transmit Line
Interface
Master
Clocking Unit
DAC
XL1/XOID1
G
H
E
F
%
FCLKR
TCLK
FCLKX
recovered
receive clock
Equalizer
Clock &
Data
Recovery
Decoder
RL1/ROID
RL2
Receive Line
Interface
DPLL
JATT
Buffer
RDATA
Automatic Transmit
Clock Switching
from
DCO-R
XL4
XL3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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