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| 型號(hào)： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁(yè)數(shù)： | 159/193頁(yè) |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
68
Rev. 1.0, 2005-06-02
3.7.9.3
Output Jitter
In the absence of any input jitter the OctalLIU
TM generates the intrinsic output jitter, which is specified in
theTable 20 below.
3.7.10
Dual Receive Elastic Buffer
For jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by
the clock & data recovery and are read out with the de-jittered clock sourced by DCO-R, see Figure 17.
If the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed.
If the receive elastic buffer is read out with the receive framer clock FCLKR of the framer interface (FCLKR is
input), the receive elastic buffer performs a clock adoption from the recovered receive clock to FCLKR.
The receive elastic buffer can buffer two data streams so that dual rail mode is possible at the receive framer
interface (RDOP/RDON). In case of single rail mode on the receive framer interface, the bipolar violation signal
BPV is buffered in the same way as the single rail signal and is supported at multi function pin RDON.
The size of the elastic buffer can be configured independently for the receive and transmit direction. Programming
of the receive buffer size is done by DIC1.RBS(1:0), of the transmit buffer size by DIC1.XBS(1:0) see Table 21:
The functions are:
Clock adoption between framer receive clock (FCLKR input) and internally generated route clock (recovered
line clock), see Chapter 3.7.9.
Compensation of input wander and jitter.
Reporting and controlling of slips
Table 20
Output Jitter (E1)
Specification
Measurement Filter Bandwidth
Intrinsic Output Jitter
(UI peak to peak)
Lower Cutoff
Upper Cutoff
ITU-T I.431
20 Hz
100 kHz
< 0.015
700 Hz
100 kHz
< 0.015
ETSI TBR 12
40 Hz
100 kHz
< 0.11
PUB 62411
10 Hz
8 kHz
< 0.015
8 Hz
40 kHz
< 0.015
10 Hz
40 kHz
< 0.015
Broadband
< 0.02
Table 21
Receive (Transmit) Elastic Buffer Modes
DIC1.RBS(1:0) (DIC1.XBS(1:0)) Mode
Frame buffer
size (bits)
Maximum of
wander (UI =
648 ns)
Average delay
after performing
a slip
Slip
Performance
00
10
E1
512
190
256
Yes
T1/J1
396
140
193
01
E1
256
100
128
T1/J1
193
74
96
10
11 (short buffer
mode)
E1
96
38
48
T1/J1
11
00
E1
Bypass of the receive (transmit) elastic buffer
No
T1/J1
Bypass of the receive (transmit) elastic buffer
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相關(guān)代理商/技術(shù)參數(shù) |
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| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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