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參數(shù)資料
| 型號(hào)： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁數(shù)： | 153/193頁 |
| 文件大小： | 10683K |
| 代理商： | PEF22508E |
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OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
62
Rev. 1.0, 2005-06-02
Recovery: In general the recovery procedure starts after detecting a logical one (digital receive interface) or a
pulse (analog receive interface) with an amplitude more than Q dB (defined by LIM1.RIL(2:0)) of the nominal
pulse. The value in the 8-bit register PCR defines the number of pulses (1 to 255) to clear the LOS alarm.
If a loss-of-signal condition is detected in long-haul mode, the data stream can optionally be cleared automatically
to avoid bit errors before LOS is indicated. The Selection is done by LIM1.CLOS = 1.
3.7.6
Receive Equalization Network
The OctalLIU
TM automatically recovers the signals received on pins RL1 and RL2 in a range of up to -43 dB for
E1 or -36 dB for T1/J1. The maximum reachable length with a 22 AWG twisted pair cable is about 1500 m for E1
and about 2000m (~6560 ft) for T1. The integrated receive equalization network recovers signals with up to -43 dB
for E1 or -36 dB for T1/J1 of cable attenuation automatically. Noise filters eliminate the higher frequency part of
the received signals. The incoming data is peak-detected and sliced to produce the digital data stream. The slicing
level is software selectable in four steps (45%, 50%, 55%, 67%), see Table 50. For typical E1 applications, a level
of 50% is used. The received data is then forwarded to the clock & data recovery unit.
Each of the OctalLIU
TM line receivers use parameters which are internally stored in a ROM. With these parameters
the maximum receiver sensitivity is only 33 dB in E1 mode.
It is also possible to use parameters stored in an internal RAM instead of those stored in the internal ROM. The
RAM parameters must be loaded before activation of the lines. The RAM is accessible over the micro controller
interface in the same way as the OctalLIU
TM registers by using a special RAM access mode. All interface modes
(Motorola, Intel, SPI or SCI) can be used for RAM access.
The activation of the RAM access mode, the load procedure of the RAM, the values of the RAM parameters and
the deactivation of the RAM access mode to have access to the registers again are not described in the data sheet
of the OctalLIU
TM.
The source code for loading the optimal parameters into the RAM is available on request. Use of these optimal
parameters improves the maximum receiver sensitivity to 43 dB in E1 mode.
3.7.7
Receive Line Attenuation Indication
Status register RES reports the current receive line attenuation
For E1 in a range from 0 to -43 dB in 25 steps of approximately 1.7 dB each.
For T1/J1 in a range from 0 to -36 dB in 25 steps of approximately 1.4 dB each.
The least significant 5-bits of this register indicate the cable attenuation in dB. These 5-bits are only valid in
combination with the most significant two bits (RES.EV(1:0) = 01
b).
3.7.8
Receive Clock and Data Recovery
The analog received signal on pins RL1 and RL2 is equalized and then peak-detected to produce a digital signal.
The digital received signal on pins RDIP and RDIN is directly forwarded to the clock & data recovery. The so called
DPLL (digital PLL) of the receive clock & data recovery extracts the route clock from the data stream received at
the RL1/2 or ROID lines. The clock & data recovery converts the data stream into a dual-rail, unipolar bit stream.
The clock and data recovery uses an internally generated high frequency clock out of the master clocking unit
based on MCLK.
The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.
3.7.9
Receive Jitter Attenuator
The receive jitter attenuator is based on the DCO-R (digital clock oscillator, receive) in the receive path. Jitter
attenuation of the received data is done in the dual receive elastic buffer. The working clock is an internally
generated high frequency clock based on the clock provided on pin MCLK. The jitter attenuator meets the E1
requirements of ITU-T I.431, G. 736 to 739, G.823 and ETSI TBR12/13 and the T1 requirements of AT&T
PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431, G.703 and G. 824.
The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly dependent on the phase
difference of the incoming clock and the jitter attenuated clock. The receive jitter attenuator can be synchronized
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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