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參數(shù)資料
| 型號： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁數(shù)： | 144/193頁 |
| 文件大小： | 10683K |
| 代理商： | PEF22508E |
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OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
54
Rev. 1.0, 2005-06-02
Figure 16
Flexible Master Clock Unit
3.5.5.1
PLL (Reset and Configuring)
If the (asynchronous) micro controller interface mode is selected by IM(1:0) the PLL must be configured
By programming of the registers GCM5 and GCM6 in “flexible master clocking mode”. Every change of the
contents of these registers - the divider factors N and M of the PLL - causes a reset of the PLL. Switching
between E1 and T1 modes in arbitrary channels causes a reset of the clock unit but not of the PLL itself.
Or by enabling of the ”fixed mode”: GCM2.VFREQ_EN = 0 (GCM2). Programming of registers GCM5 and
GCM6 is not necessary. Any programming of GCM5 and GCM6 does NOT cause a reset of the PLL. Switching
between E1 and T1 modes (for all channels) causes a reset of the clock unit but not of the PLL itself.
The SPI and SCI are synchronous interfaces and therefore need defined clocks immediately after reset, before
any configuration is done. So to enable access to serial interfaces, the clock MCLK must be active and must have
a defined frequency before reset becomes inactive. Dependent on the MCLK frequency the internal PLL must be
configured if the SCI- or SPI-Interface mode is selected by IM(1:0)
By strapping of the pins D(15:5) if “fixed mode” is not enabled (GCM2.VFREQ_EN = 1), see also Table 2.
Because “fixed mode” is not enabled after reset, pinstrapping at D(15:5) is always necessary! Every new value
at this pins causes a reset of the PLL. Configuring by the registers GCM5 and GCM6 is not taken into account
and causes not a reset of the PLL
Or by enabling of the ” fixed mode”.This is only allowed if the values of N and M defined by pinstrapping are
identical to that values which are internally used for the “fixed mode”. That avoids changing of N and M by
switching into the ”fixed mode” and therefore a new reset of the PLL. (A new reset of the PLL can cause a hang
up of the whole system!) In ”fixed mode” the values are: N = 33
10, M = 010 so that the pinstrapping must be:
D(10:5) = HLLLLH, D(15:11) = LLLLL. In ”fixed mode” programming of registers GCM1 to GCM8 is no
longer necessary and values at the pins D(15:5) are no longer taken into account and causes NOT a reset of
the PLL. A switching between E1 and T1 modes causes a reset of the clock unit but not of the PLL itself.
The configuration of the PLL by pinstrapping (see Table 2) in case of serial interface modes is done in the same
way as by using the registers GCM5 and GCM6 if asynchronous micro controller interface mode (Intel or Motorola)
is selected. So calculation of the pinstrapping values can be done also by using the formulas in GCM6 or by using
the “flexible Master Clock Calculator” which is part of the software support of the OctalLIU
TM, see Chapter 8.3. If
the serial interfaces are selected, pinstrapping of D(15:5) configure the PLL directly, so changes causes always a
reset of the PLL.
The conditions to trigger a reset of the central clock PLL are listed in Table 11. Every reset of the PLL causes a
reset of the clock system.
Flexible Master Clock Unit
GCM1...GCM8
MCLK
E1 Clocks
T1 / J1
Clocks
OctalFALC__F0116
PLL
channel
1 to 8
IM(1:0)
D(15:5)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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