參數(shù)資料
型號(hào)： P83CL882
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無(wú)鉛汽油電話(huà)控制器
文件頁(yè)數(shù)： 58/88頁(yè)
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
58
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.9.2
M
ODEM INTERFACE
The modem block has the following modem interface
signals,
MIN:
MSK Manchester coded input signal from the data
slicer
MOUT0 to MOUT2:
3-bit Manchester coded output
signal of the modem.
The MSK receiver input can be inverted by programming
bit MSKPOL (WDCON.2; see Section 6.7.1):
MSKPOL = 0: direct connection between the MIN pin
and MSK receiver
MSKPOL = 1: inverted connection between the MIN pin
and MSK receiver.
The mute signals RX_MUTE and TX_MUTE must be
handled by software according to the progress in the data
transfer. Any standard I/O port pin can be used for this
purpose.
6.9.3
S
YNCHRONISATION
When enabled the receiver samples MIN with a frequency
f
sample
= 8
×
baud rate. The sampled values are shifted
intoan8-bitshiftregister.Thisregisterisregularlychecked
to determine whether it contains samples that fulfil the
Manchester coding rule, i.e. whether there is
a LOW-to-HIGHoraHIGH-to-LOWtransitioninthemiddle
of the bitcell.
Figure 26a shows a regular, full synchronized bitcell.
Figure 26b shows a regular, not synchronized bitcell, this
phase shift will be corrected in the next received bitcell.
Figure 26c (data is faster than internal timebase)
and Fig.26d (data is slower than internal timebase)
represent a non-valid, not synchronized bitcell. In the next
received bitcell the data will be re-synchronized but the
current data bit does not fulfil the Manchester coding rule
and will be lost.
The receiver searches for three consecutive sets of
8 samples that fulfil the Manchester coding rule.
If these three sets have been found the clock is locked
(MRL = 1) and the receiver starts looking for the
Manchester preamble pattern.
From this point on the receiver uses a Phase-Locked
Loop (PLL) to adjust the synchronisation after each
received Manchester bit. To detect a sample shift the
receiver uses all 8 samples. If the data is at maximum, one
sample out of phase, the receiver is able to resynchronize
without losing data. If the data is up to three samples out
of phase the receiver can still resynchronize but the data
is lost. The correction is done by shifting only one sample
per bitcell. This means up to three bit cells are needed for
full resynchronisation. If the receiver is not able to
establish resynchronization within three bitcells the lock bit
(MRL) will be reset.
Therefore the MSK modem can receive correct input data
with maximum jitter of 1/f
sample
.
MGT299
MIN
1 2 3 4 5 6 7 8
(a)
1 2 3 4 5 6 7 8
(c)
1 2 3 4 5 6 7 8
(d)
1 2 3 4 5 6 7 8
(b)
MIN
MIN
MIN
Fig.26 Schematic representation of a bitcell.
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