參數(shù)資料
型號(hào): P83CL882
廠商: NXP Semiconductors N.V.
英文描述: 80C51 Ultra Low Power ULP telephony controller
中文描述: 80C51的超低功耗無(wú)鉛汽油電話控制器
文件頁(yè)數(shù): 36/88頁(yè)
文件大?。?/td> 328K
代理商: P83CL882
2001 Jun 19
36
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
Table 42
Timer 0 and Timer 1 mode select
n = 0 or 1.
6.5.5
S
YSTEM
C
ONTROL
R
EGISTER
(SYSCON)
Table 43
System Control Register (SFR address B4H; reset value = 0000 0000)
Table 44
Description of SYSCON bits
Table 45
Timer 1 input source select modes
Table 46
Timer 0 input source select modes
M1
M0
DESCRIPTION
0
0
1
0
1
0
8048-type timer.
TLn serves as 5-bit prescaler
16-bit Timer/Counter.
THn and TLn are cascaded; there is no prescaler
8-bit auto-reload timer/counter.
THn holds a value which is to be reloaded into TLn
each time it overflows.
Timer 0.
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits;
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
Timer 1.
Timer/Counter 1 stopped.
1
1
7
6
5
4
3
2
1
0
T1SRC1
T1SRC0
T0SRC1
T0SRC0
SELECT
XTM
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
T1SRC1
T1SRC0
T0SRC1
T0SRC0
SELECT
XTM
Timer 1 clock source select bit 1 and 0; see Table 45
Timer 0 clock source select bit 1 and 0; see Table 46
do not use
comparator select bit; see Section 6.1
oscillator disable bit; see Section 6.1
T1SRC1
T1SRC0
DESCRIPTION
0
0
1
1
0
1
0
1
f
psc
is the Timer 1 clock input
T1 is the Timer 1 clock input
the ROMreq signal is the Timer 1 clock input
f
per
is the Timer 1 clock input
T0SRC1
T0SRC0
DESCRIPTION
0
0
1
1
0
1
0
1
f
psc
is the Timer 0 clock input
T0 is the Timer 0 clock input
the instruction request signal is the Timer 0 clock input
f
per
is the Timer 0 clock input
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