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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 17/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
17
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.2.3
I
DLE AND
P
OWER
-
DOWN OPERATION
Idle and Power-down are power saving modes of the
microcontroller that can be activated when no CPU activity
is required. These two modes are extremely useful for the
asynchronous CPU, because they offer the possibility to
profit from the speed of the CPU and to save power as
soon as the task is finished. Idle mode stops the code
execution of the CPU, but the internal oscillator remains
active, and also all peripheral functions connected to the
on-chip clock signal. Unused blocks can be switched off
independently. However, during Power-down mode the
clock oscillator is stopped and therefore also all peripheral
blocks will stop their activity.
6.2.3.1
Idle mode
The following functions remain active during Idle mode:
Timers 0, 1 and 2
Wake-up counter
Watchdog Timer counter
MSK modem
I
2
C-bus interface
External interrupt.
The instruction that sets PCON.0 (PCON SFR) is the last
instruction executed in the normal operating mode before
theIdlemodeisactivated.TheRAMandalloftheregisters
are preserved and maintain their data during Idle mode:
the CPU status, the stack pointer, program counter,
program status word and accumulator.
There are two ways to terminate the Idle mode:
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware thus terminating the Idle mode.
The interrupt is serviced, and following the RETI
instruction,thenextinstructiontobeexecutedwillbethe
one following the instruction that put the device in the
Idle mode.
The second way of terminating the Idle mode is with an
internal or external hardware reset. Reset redefines all
SFRs but does not affect the on-chip RAM. The source
of an internal reset is the Watchdog Timer if the preset
delay has expired.
6.2.3.2
Power-down mode
The instruction that sets PCON.1 (PCON SFR) is the last
instruction executed in the normal operating mode before
the Power-down mode is activated. During Power-down
mode, the RAM and all of the registers maintain their data:
the CPU status, the stack pointer, program counter,
program status word and accumulator.
There are two ways to terminate the Power-down mode:
Activation of any of the interrupts listed below will cause
PCON.1 to be cleared by hardware thus terminating the
Power-down mode. The interrupt is serviced, and
following the RETI instruction, the next instruction to be
executedwill betheone followingtheinstruction thatput
the device in the Power-down mode. Interrupts which
can generate a wake-up from power-down:
– External interrupts (INT0 to INT9)
– Timer 0 and Timer 1: only when pins T0 and T1 are
used as the external timer source input (SYSCON
SFR bits 7 to 4)
The second way of terminating the Power-down mode is
with an internal or external hardware reset. Reset does
not affect the on-chip RAM, but all SFRs are set to the
default value.
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