參數(shù)資料
型號： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無鉛汽油電話控制器
文件頁數(shù)： 33/88頁
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
33
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.5.1
C
LOCK SOURCE SIGNALS OF
T
IMER
0
AND
T
IMER
1
Inallfour modesTimer 0and Timer 1canbeconfiguredto
increment from different internal and external clock
sources. The TMOD and SYSCON registers must be
written to determine the source of the clock signal. After
reset the clock source for both timers is connected to the
internal clock signal from PSC1 (f
psc
). The second of four
possible clock sources is connected to the other internal
clock signal coming from PSC2 (f
per
).
The clock input on both timers has a multiplexer to choose
from 4 different clock sources. If the multiplexers are
switched to another input by setting user controllable bits
in the SYSCON SFR (bits 7 to 4), the timers can also
increment on the other on-chip clock signal coming from
PSC2 (f
per
).
In counter mode the timers are incrementing on transitions
on the T0 and T1 input pins. First way to enter this mode
is by setting control bits C/T (TMOD.6 and 2). Second way
is to configure SYSCON to switch the input multiplexer to
the clock input signal T1 or T0 while C/T is logic 0. The
latter is also functional even when there is no system clock
available. This means when a clock source is supplied on
a port pin the Timer 1 or 0 can count and generate
interrupts even when the chip is in Power-down mode.
Maximum input signal frequency and duty cycle for the
timer in counter mode is given in Chapter 11.
The last multiplexer input to Timer 1 and Timer 0 is an
auxiliary mode which can be used to obtain the operation
speed from the handshake CPU. If this mode is activated
for the Timer 1 input source, the timer increments on every
ROM request. This means the timer increments by three
for a three byte instruction and by two for a two byte
instructionetc.IftheauxiliarymodeisactivatedforTimer 0
the timer increments on every instruction executed by
the CPU. This means the timer register holds the number
of instructions executed in a certain time frame. This can
be used to obtain the number of Mips at which the
processor is running. The SYSCON register is described
in Section 6.5.5.
6.5.2
O
PERATING MODES OF
T
IMER
0
AND
T
IMER
1
The ‘Timer’ or ‘Counter’ function is selected by control
bits C/T in the Special Function Register TMOD. These
two Timer/Counters have four operating modes, which are
selected by bit-pairs (M1 and M0) in TMOD.
Modes 0, 1, and 2 are the same for both Timers/Counters.
Mode 3 configures Timer 0 while Timer 1 is disabled.
The four operating modes are:
Mode 0 Putting either Timer 0 or Timer 1 into Mode 0
makes it look like an 8048 timer, which is an 8-bit
counter with a divide-by-32 prescaler. Figure 16
shows the Mode 0 operation as it applies to
Timer 1. In this mode, the timer register is
configured as a 13-bit register. As the count rolls
over from all logic 1s to all logic 0s, it sets the
timer interrupt flag TF1. Timer 1 is enabled when
TR1 = 1. With GATE = 0, it is continuously
counting, setting GATE = 1, the timer is
controlled by the external input INT1, to facilitate
pulse width measurements. TR1 is a control bit in
the SFR TCON (see Section 6.5.3). GATE is in
TMOD. The 13-bit register consists of all 8 bits of
TH1 and the lower 5 bits of TL1. The upper 3 bits
of TL1 are indeterminate and should be ignored.
Setting the run flag (TR1) does not clear the
registers. Mode 0 operation is the same for
Timer 0 as for Timer 1. Substitute TR0, TF0, and
INT0 for the corresponding Timer 1 signals in
Fig.16. There are two different GATE bits, one for
Timer 1 (TMOD.7) and one for Timer 0
(TMOD.3).
Mode 1 Is the same as Mode 0, except that the timer
register is being run with all 16 bits.
Mode 2 Configures the timer register as an 8-bit counter
(TL1) with automatic reload, as shown in Fig.17.
Overflow from TL1 not only sets TF1, but also
reloads TL1 with the contents of TH1, which is
preset by software. The reload leaves TH1
unchanged. Mode 2 operation is the same for
Timer/Counter 0.
Mode 3 Timer 1 in Mode 3 simply holds its count. The
effect is the same as setting TR1 = 0. Timer 0 in
Mode 3 establishes TL0 and TH0 as two
separate counters. The logic for Mode 3 on
Timer 0 is shown in Fig.18. TL0 uses the Timer 0
control bits: C/T, GATE, TR0, INT0, and TF0.
TH0 is locked into a timer function and takes over
the use of TR1 and TF1 from Timer 1. Thus, TH0
now controls the Timer 1 interrupt. Mode 3 is
provided for applications requiring an extra 8-bit
timer on the counter. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it
out of and into its own Mode 3 or in any
application not requiring an interrupt.
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