參數(shù)資料
型號： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無鉛汽油電話控制器
文件頁數(shù)： 53/88頁
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
53
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid
status code can be read from S1STA. This status code is
used to vector to an interrupt service routine, and the
appropriate action to be taken for each of these status
codes is detailed in the table. The Slave transmitter mode
may also be entered if arbitration is lost while SIO1 is in the
Master mode.
IftheAA bitisresetduringatransfer,SIO1willtransmitthe
last byte of the transfer and enter state C0H or C8H. SIO1
is switched to the not addressed Slave mode and will
ignore the master receiver if it continues the transfer. Thus
the master receiver receives all logic 1s as serial data.
While AA is reset, SIO1 does not respond to its own slave
address or a general call address. However, the I
2
C-bus is
still monitored, and address recognition may be resumed
at any time by setting AA. This means that the AA bit may
be used to temporarily isolate SIO1 from the I
2
C-bus.
6.8.6
F
UNCTIONAL DESCRIPTION
I
2
C-
BUS INTERFACE
6.8.6.1
Input filter
Input signals SDA and SCL from I/O pad cells are
synchronized with f
per
, and spikes shorter than three clock
periods are filtered out.
6.8.6.2
Arbitration and control logic
IntheMastertransmittermode,thearbitrationlogicchecks
that every transmitted logic 1 actually appears as a logic 1
on the I
2
C-bus. If another device on the bus overrules
a logic 1 and pulls the SDA line LOW, arbitration is lost,
and SIO1 immediately changes from master transmitter to
slave receiver. SIO1 will continue to output clock pulses
(on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the Master receiver mode.
Loss of arbitration in this mode can only occur while SIO1
is returning a ‘not acknowledge’ (logic 1) to the bus.
Arbitration is lost when another device on the bus pulls this
signal LOW. Since this can occur only at the end of a serial
byte, SIO1 generates no further clock pulses.
The synchronization logic will synchronize the serial clock
generator with the clock pulses on the SCL line from
another device. If two or more master devices generate
clock pulses, the ‘mark’ duration is determined by the
device that generates the shortest ‘marks,’ and the ‘space’
duration is determined by the device that generates the
longest ‘spaces’.
A slave may stretch the space duration to slow down the
bus master. The space duration may also be stretched for
handshaking purposes. This can be done after each bit or
after a complete byte transfer. SIO1 will stretch the SCL
space duration after a byte has been transmitted or
received and the acknowledge bit has been transferred.
The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
This block also controls all of the signals for serial byte
handling. It provides the shift pulses for S1DAT, enables
the comparator, generates and detects START and STOP
conditions, receives and transmits acknowledge bits,
controls the Master and Slave modes, contains interrupt
request logic and monitors the I
2
C-bus status.
6.8.6.3
Bus clock generator
This programmable clock pulse generator provides the
SCL clock pulses when SIO1 is in the Master transmitter
or Master receiver mode. It is switched off when SIO1 is in
a Slave mode. The output frequency is dependent on the
CR bits in the control register. The output clock pulses
have a 50% duty cycle unless the clock generator is
synchronized with other SCL clock sources as described
above.
6.8.6.4
Address Register (S1ADR) and comparator
This 8-bit SFR may be loaded with the 7-bit slave address
to which SIO1 will respond when programmed as a slave.
The least significant bit is used to enable the general call
address recognition.
The comparator compares the received 7-bit slave
address with its own slave address. It also compares the
first received byte with the general call address. If an
equality is found, the appropriate status bits are set and an
interrupt is requested.
6.8.6.5
Data Shift Register (S1DAT)
This 8-bit SFR contains a byte of serial data to be
transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been
received, the first bit of received data is located at the MSB
of S1DAT. While data is being shifted out, data on the bus
is simultaneously being shifted in; S1DAT always contains
the last byte present on the bus. Thus, in the event of lost
arbitration, the transition from master transmitter to slave
receiver is made with the correct data in S1DAT.
相關(guān)PDF資料
PDF描述
P83CL883T TELX microcontrollers for CT0 handset/basestation applications
P83CL884T TELX microcontrollers for CT0 handset/basestation applications
P87CL883T TELX microcontrollers for CT0 handset/basestation applications
P87CL884T TELX microcontrollers for CT0 handset/basestation applications
P8503BMG N-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P83CL882T/001 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 Ultra Low Power ULP telephony controller
P83CL883T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TELX microcontrollers for CT0 handset/basestation applications
P83CL883T/XXX 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MICROCONTROLLER|8-BIT|8051 CPU|CMOS|SOP|28PIN|PLASTIC
P83CL884T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TELX microcontrollers for CT0 handset/basestation applications
P83CL884T/XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*