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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 18/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
18
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.2.3.3
Power Control Register (PCON)
The reduced power modes are activated by software using this special function register. PCON is not bit addressable.
The reset value of PCON = 0000 0000.
Table 10
Power Control Register (SFR address 87H)
Bits PCON[7:2] are reserved and must be kept to logic 0.
Table 11
Reduced power modes selection
6.2.4
CPU
START
-
UP TIMING
6.2.4.1
CPU start-up after reset
Three possibilities on how the CPU can start executing code after a reset phase are described below.
When the CPU is triggered to wake-up after a power-on reset (see Fig.8), the clock oscillator usually needs some time
to ramp up. To allow the oscillator to stabilize the CPU contains a down counter for a fixed delay of 1024 + 16 clock
cycles. After this delay the CPU starts with code execution.
When CPU start-up is initiated from an external reset (see Fig.9), the down counter is not initialized and the time between
reset going active and first code execution can be maximum 16400 clock cycles.
When a CPU start-up is after a Watchdog Timer reset (see Fig.8), the RST pin will be pulled low for 1024 clock cycles.
Another 16 clocks later the CPU will start executing code.
6.2.4.2
CPU start-up after power-down
After wake-up from Power-down mode (see Fig.10) the user has the possibility to shorten the start-up time by
programming the Wake-up Counter Register (WKCON). This can be useful when an external clock source is used
instead of the on-chip oscillator, or when the accuracy of the time reference is not needed immediately after a restart.
This feature enables power saving and fast wake-up in applications where the CPU frequently goes into Power-down
mode. The wake-up delay can be calculated as shown in Table 13.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
PD
IDL
PD
0
0
1
1
IDL
0
1
0
1
DESCRIPTION
CPU running
activates the Idle mode
activates the Power-down mode
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