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參數(shù)資料
| 型號(hào)： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 38/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
38
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.6.1.2
Timer 2 Mode Register (T2MOD)
Table 50
Timer 2 Mode Register (SFR address C9H)
Table 51
Description of T2MOD bits
6.6.1.3
T2H and T2L Registers
These registers are normal registers in the SFR space. They are the actual timer/counter registers. On the fly reading
can give a wrong value since T2H can be changed after T2L is read and before T2H is read. This situation is indicated
by flag T2RD in T2MOD SFR. In all cases the two 8-bit registers operate as one 16-bit timer/counter register.
6.6.1.4
T2RCH and T2RCL Registers
These registers are normal registers in the SFR space. They are the capture and reload registers depending on the
chosen operation mode. In the Capture mode the T2RCH/T2RCL registers are loaded with the value of the T2H/T2L
registers. In the reload mode the T2H/T2L registers are loaded with the value of the T2RCH/T2RCL registers.
7
6
5
4
3
2
1
0
T2RD
C/T2OE
CP/DCEN
BIT
SYMBOL
T2RD
DESCRIPTION
7 to 3
2
Reserved; must be kept to logic 0.
Timer 2 read flag.
Set/reset by hardware only. This bit is set by hardware if a T2L read
operation is followed by an increment of T2H before a T2H read operation. This bit is
reset on the trailing edge of the next T2L read. This bit is used to indicate that the 16-bit
Timer 2 register is not read properly since the T2H part was incremented by hardware
before it was read.
Timer 2 output enable bit.
Set by software only. When set and T2CON.TF2 is reset
and T2CON.EXF2 is reset, output T2 outputs a clock signal. When this condition is not
met, output T2 outputs a logic 1. The clock output is half the overflow frequency of
Timer 2.
Down count enable flag.
Set by software only. When this bit is set and input T2EX is
set Timer 2 can be configured (in Auto-reload mode) as an up counter. When this bit is
reset or input T2EX is reset, Timer 2 can be configured (in Auto-reload mode) as a down
counter.
1
C/T2OE
0
CP/DCEN
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