參數(shù)資料
型號： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無鉛汽油電話控制器
文件頁數(shù)： 35/88頁
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
35
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.5.3
T
IMER
/C
OUNTER
0
AND
1 C
ONTROL
R
EGISTER
(TCON)
Table 38
Timer/Counter 0 and 1 Control Register (SFR address 88H)
Table 39
Description of TCON bits
Note
1.
If the Timer 0 or Timer 1 is not enabled (TR0 or TR1), the clock to Timer 0/1 is switched off for power saving.
6.5.4
T
IMER
/C
OUNTER
0
AND
1 M
ODE
C
ONTROL
R
EGISTER
(TMOD)
Table 40
Timer/Counter 0 and 1 Mode Control Register (SFR address 89H)
Table 41
Description of TMOD bits
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
BIT
SYMBOL
DESCRIPTION
7
TF1
Timer 1 overflow flag.
Set by hardware on timer/counter overflow; cleared by hardware
when processor vectors to interrupt routine, or clearing the bit in software.
Timer 1 run control bit.
Set/cleared by software to turn timer/counter on/off; note 1.
Timer 0 overflow flag.
Set by hardware on timer/counter overflow; cleared by hardware
when processor vectors to interrupt routine, or by clearing the bit in software.
Timer 0 run control bit.
Set/cleared by software to turn timer/counter on/off; note 1.
Interrupt 1 edge flag.
Set by hardware when external interrupt edge detected; cleared
when interrupt processed.
Interrupt 1 type control bit.
Set/cleared by software. If IT1 = 1, then external interrupt
is LOW-level triggered. If IT1 = 0, then external interrupt is falling edge triggered.
Interrupt 0 edge flag.
Set by hardware when external interrupt edge detected; cleared
when interrupt processed.
Interrupt 0 type control bit.
Set/cleared by software. If IT0 = 1, then external interrupt
is LOW-level triggered. If IT0 = 0, then external interrupt is falling edge triggered.
6
5
TR1
TF0
4
3
TR0
IE1
2
IT1
1
IE0
0
IT0
7
6
5
4
3
2
1
0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
BIT
SYMBOL
DESCRIPTION
7
GATE
Gating control.
When set Timer/Counter 1 is enabled only while INT1 pin is HIGH and
TR1 control pin is set; when cleared Timer 1 is enabled whenever TR1 control bit is set.
Timer or counter selector.
Cleared for timer operation (counts on f
PSC
); set for counter
operation (input from T1 input pin).
Timer 1 mode select.
See Table 42.
6
C/T
5
4
3
M1
M0
GATE
Gating control.
When set Timer/Counter 0 is enabled only while INT0 pin is HIGH and
TR0 control pin is set; when cleared Timer 0 is enabled whenever TR0 control bit is set.
Timer or counter selector.
Cleared for timer operation (counts on f
PSC
); set for counter
operation (input from T0 input pin).
Timer 0 mode select.
See Table 42.
2
C/T
1
0
M1
M0
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