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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 14/88頁 |
| 文件大小： | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
14
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.2
The CPU
6.2.1
G
ENERAL
Ultra Low Power (ULP), points to the special 80C51 CPU
architecture used in this device allowing significant power
saving.
The CPU of the P83CL882 is realized in the Philips
exclusiveasynchronoushandshakingtechnology,whichis
completely different to usual implementations of this core.
The processor does not need a clock signal to run
instructions. Every function within the CPU is self timed
and always runs at the maximum speed that the silicon die
under the current operating conditions allows (supply
voltage and temperature). The advantage is the
combination of a high computing power with reduced
average power consumption and low EMC noise
generation. Details about speed and energy consumption
per instruction can be found in Chapter 8.
Summary of the CPU features:
No CPU clock is needed
Only useful bytes are fetched from the program
memory; the dummy read cycles which exist in the
standard 80C51 have been eliminated to save power
To further speed up the program execution; there is
always a pre-fetch of the next byte of code from memory
during the execution of the current instruction; in the
case of a jump the pre-fetched byte is discarded
In Idle mode the CPU power is reduced to leakage; only
the enabled peripheral blocks consume power but can
be switched off independently
The only need for a clock is as a timing reference for
timers/counters and to generate the timing for the
I/O lines to synchronise with the off-chip world.
6.2.2
R
ESET OPERATION
There are two possibilities to reset the CPU (see Fig.7):
Watchdog Timer reset
External reset via I/O pin RST.
Ifaninternalresetisexecuted(WatchdogTimer),thereset
pin RST will be pulled to ground which can be used as
reset signal for other ICs. The reset pin is LOW for at least
1024 clock cycles, and released 16 clock cycles prior to
first code fetch (see Figs 8 and 9).
handbook, full pagewidth
internal
reset
WATCHDOG
TIMER
Rpu
VSS
VDD
RST
(external
reset)
LOGIC
MGU267
Fig.7 Reset sources.
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