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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 12/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
12
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.1.3.1
Prescaler Register (PRESC)
Reset value of PRESC SFR is XXX0 0000 (division factor 1 for PSC1 and PSC2).
Table 5
Prescaler Register (SFR address F3H)
Table 6
Description of PRESC bits
Table 7
Division factors for PSC1 and PSC2
6.1.4
A
UXILIARY CLOCK SIGNAL MODES
The 3 most significant bits in the Prescaler Register (see Tables 5 and 6) are used to enable additional clocking options.
A multiplexer is implemented (see Fig.6) to choose between f
psc
and f
per
as the source for AUXCLK. The multiplexer is
operated by bit AUXSW (PRESC.6). With bit EXTCK (PRESC.7) the AUXCLK is fed to pin P1.4 (CLKOUT) for external
use (initialize the port accordingly). Setting bit SYNC (PRESC.5) connects the AUXCLK to the instruction request input
of the CPU. In this way the CPU is synchronised to the clock and an instruction is executed at every clock pulse of
AUXCLK. In order to obtain exactly one instruction per clock cycle the period for AUXCLK must always be longer than
the length of the slowest instruction.
7
6
5
4
3
2
1
0
EXTCK
AUXSW
SYNC
PRESC.4
PRESC.3
PRESC.2
PRESC.1
PRESC.0
BIT
SYMBOL
DESCRIPTION
7
6
EXTCK
AUXSW
Switches AUXCLK to device pin P1.4 (CLKOUT).
Auxiliary Clock Switch.
If AUXSW = 0; then AUXCLK equals f
psc
. If AUXSW = 1; then
AUXCLK equals f
per
.
Switches the CPU to Synchronous mode.
PRESC.[4:0] These bits define the division factors for PSC1 and PSC2; see Table 7.
5
SYNC
4 to 0
DIVISION FACTOR
PRESC.4
PRESC.3
PRESC.2
PRESC.1
PRESC.0
PSC2
(f
osc
/f
per
)
1
2
4
8
PSC1
(f
osc
/f
psc
)
1
2
4
6
8
10
12
16
0
0
1
1
X
X
X
X
X
X
X
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
0
1
0
1
0
1
0
1
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