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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 51/88頁 |
| 文件大小： | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
51
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
Table 67
Symbols used in Table 66
SYMBOL
DESCRIPTION
SLA
R
W
ACK
ACK
DATA
MST
SLV
TRX
REC
7-bit slave address
Read bit
Write bit
acknowledgement (acknowledge bit = logic 0)
no acknowledgement (acknowledge bit = logic 1)
8-bit data byte to or from I
2
C-bus
master
slave
transmitter
receiver
6.8.5
M
ODES OF OPERATION
The I
2
C-bus logic may operate in any of the following four
modes:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
As a master, the I
2
C-bus logic will generate all of the serial
clock pulses and the START and STOP conditions.
A transfer is ended with a STOP condition or with
a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer,
the I
2
C-bus will not be released.
Two types of data transfers are possible on the I
2
C-bus:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received
byte.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted
by the master. The slave then returns an acknowledge
bit. Next follows the data bytes transmitted by the slave
to the master. The master returns an acknowledge bit
after each received byte except the last byte. At the end
of the last received byte, a ‘not acknowledge’ is
returned.
In a given application, SIO1 may operate as a master and
as a slave. In the Slave mode, the SIO1 hardware looks for
its own slave address and the general call address. If one
of these addresses is detected, an interrupt is requested.
When the microcontroller wishes to become the bus
master, the hardware waits until the bus is free before the
Master mode is entered so that a possible slave action is
notinterrupted.IfbusarbitrationislostintheMastermode,
SIO1 switches to the Slave mode immediately and can
detect its own slave address in the same serial transfer.
6.8.5.1
Master transmitter mode
Serial data is output through SDA while SCL outputs the
serial clock. The first byte transmitted contains the slave
address (7-bit SLA) of the receiving device and the data
direction bit. In this case the data direction bit (R/W) will be
a logic 0 (W). Serial data is transmitted 8 bits at a time.
After each byte is transmitted, an acknowledge bit is
received. START and STOP conditions are output to
indicate the beginning and the end of a serial transfer.
In the Master transmitter mode, a number of data bytes
can be transmitted to the slave receiver. Before the Master
transmitter mode can be entered, S1CON must be
initialized with the ENS1 bit set and the STA, STO and
SI bits reset. ENS1 must be set to enable the SIO1
interface. If the AA bit is reset, SIO1 will not acknowledge
its own slave address or the general call address if they
are present on the bus. This will prevent the SIO1 interface
from entering a Slave mode.
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