參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù)： 80/86頁
文件大?。?/td> 701K
代理商： MT90866AG2
MT90866
Data Sheet
80
Zarlink Semiconductor Inc.
Figure 40 - Local Serial Stream Input Timing
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel the time taken to discharge C
L
.
AC Electrical Characteristics
- Local and Backplane Tristate Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
STo/STio Delay - Active to High-Z
- High-Z to Active
2.048 Mb/s (local)
4.096 Mb/s (local)
8.192 Mb/s (local)
8.192 Mb/s (backplane)
16.384 Mb/s (backplane)
Output Driver Enable (ODE) Delay
- High-Z to Active
2.048 Mb/s (local)
4.096 Mb/s (local)
8.192 Mb/s (local)
8.192 Mb/s (backplane)
16.384 Mb/s (backplane)
Output Driver Disable (ODE) Delay
- Active to High-Z
2.048 Mb/s (local)
4.096 Mb/s (local)
8.192 Mb/s (local)
8.192 Mb/s (backplane)
16.384 Mb/s (backplane)
t
DZ,
t
ZD
-12-
-12-
-12-
-1-
-1-
3.5-
3.5-
3.5-
7+
7+
ns
ns
ns
ns
ns
R
L
=1K, C
L
=30pF,
See Note 1.
2
t
ZD_ODE
37
37
37
20
20
ns
ns
ns
ns
ns
2
t
DZ_ODE
20
20
20
20
20
ns
ns
ns
ns
ns
STi (2 Mb/s)
Local input
STi (4 Mb/s)
Local input
STi (8 Mb/s)
Local input
V
TT
Bit 6
Ch 0
Bit 5
Ch 0
Bit 4
Ch 0
Bit 3
Ch 0
Bit 0
Ch 0
Bit 1
Ch 0
Bit 7
Ch 0
t
SIS8
t
SIH8
t
SAMP8
FRAME_A_io
FRAME_B_io
C8_A_io
C8_B_io
(Input)
t
SIS4
t
SIH4
Bit 7
Ch 0
Bit 6
Ch 0
Bit 0
Ch63
V
TT
Bit 7
Ch 0
V
TT
Bit 0
Ch31
t
SIS2
t
SIH2
t
SAMP4
t
SAMP2
(Input)
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