參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 34/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
34
Zarlink Semiconductor Inc.
17.0 DPLL Functional Description
Figure 13 - DPLL Functional Block Diagram
17.1 Reference Select and Frequency Mode MUX Circuits
The DPLL accepts two simultaneous reference input signals and operates on their rising edges. Either the primary
reference (PRI_REF) signal or the secondary reference (SEC_REF) signal can be selected to be the reference
signal (REF) to the PLL circuit. The appropriate frequency mode input (either FREQ_MOD_PRI or
FREQ_MOD_SEC) is selected to be the input of the PLL Circuit. The selection is done by the State Machine Circuit
based on the current state.
The FREQ_MOD_PRI and the FREQ_MOD_SEC are 2-bit wide inputs which reflect the value in the FP1-0 and
FS1-0 bits of the DOM1 register. The primary and the secondary references operate independently from each other
and can have different frequencies. Switching the reference from one frequency to another does not require the
device reset to be applied. Table 20 on page 55 shows input frequency selection for the primary and secondary
reference respectively.
PLL
(Fig 17)
PRI_REF
SEC_REF
CT Clock
and Frame
Monitor
C8_A_i
FAIL_A
State
Machine
(Fig 16)
REF_SEL
PRI_LOS Pin
SEC_LOS Pin
MTIE_RESET
(MRST bit in DOM2)
PHASE_OFFSET
(POS0-6 bits in DPOA)
SKEW_CONTROL
(SK0-2 bits in DPOA)
C64
CT_C8
(
C8_A_o
)
or
(
C8_B_o
)
CT_FRAME
(
FRAME_A_o
)
or
(
FRAME_B_o
)
C1M5o
HOLDOVER_RESET
(HRST bit in DOM2)
Reference
Select
MUX
Reference
Monitor
Reference
Monitor
P
S
CT Clock
and Frame
Monitor
C8_B_i
FAIL_B
AUTODETECT
(Selected by FDM0-1 bits in DOM2)
M
FREQ_MOD_PRI
(FP1-0 bits in DOM1)
FREQ_MOD_SEC
(FS1-0 bits in DOM1)
Frequency
Mode
MUX
M
HOLDOVER
MTIE_START
FREQ_MOD
REF_SELECT
LOS_PRI
LOS_SEC
FAIL_SEC
FAIL_PRI
REF
(RPS bit in DOM1)
(Selected by SP3-0 bits
in DOM1)
(Selected by SS3-0 bits
in DOM1)
APLL
CLK80M
C20i
MTIE_DONE
Frame
Select
MUX
FRAME_A_i
FRAME_B_i
FRAME
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