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參數(shù)資料
| 型號(hào)： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁(yè)數(shù)： | 77/86頁(yè) |
| 文件大小： | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
77
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: To meet the H.110 output timing requirement, the output delay time can be reduced further by programming the backplane output
advancement registers (BOA0 - 3).
* Note 2: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel the time taken to discharge C
L
.
Figure 37 - Backplane Serial Stream Timing when the Data Rate is 8 Mb/s
AC Electrical Characteristics
- Backplane Serial Streams with Data Rate of 8 Mb/s
Characteristic
1
STio0-31 Input Data Sample Point
2
STio0-31 Input Setup Time
3
STio0-31 Input Hold Time
4
STio0-31 Output Delay
Active to Active
5
Per Channel boundary HiZ
Sym.
t
SAMP8
t
CIS8
t
CIH8
t
DOD8
Min.
91.5
5+
5+
1-
Typ.
91.5
Max.
91.5
Units
ns
ns
ns
ns
Test Conditions
5+
C
L
= 30 pF, Note 1
t
DOZ8
t
ZDO8
10
10
ns
ns
R
L
=1K, C
L
=30 pF,
Note 2
FRAME_A_io,
FRAME_B_io
(INPUT)
C8_A_io,
C8_B_io
(8.192 MHz)
(INPUT)
STio (8 Mb/s)
Backplane input
STio (8 Mb/s)
Backplane output
V
TT
Bit 1
Ch 0
Bit 2
Ch 0
Bit 3
Ch 0
Bit 4
Ch 0
Bit 7
Ch127
Bit 6
Ch127
Bit 0
Ch 0
t
CIS8
V
TT
Bit 4
Ch 0
Bit 3
Ch 0
Bit 2
Ch 0
Bit 1
Ch 0
Bit 0
Ch 0
Bit 7
Ch127
Bit 6
Ch127
t
DOZ8
t
DOD8
t
CIH8
t
SAMP8
t
ZDO8
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