參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 73/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
73
Zarlink Semiconductor Inc.
Figure 32 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Note 1:
No jitter presented on input reference clock.
Figure 33 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz
AC Electrical Characteristics
- Local Frame Pulse and Clock Timing,
ST_CKo = 4.096MHz
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
Local Frame Boundary Offset
1
t
LFBOS
17.5+
ns
C
L
=30pF
2
ST_FPo0/1 Width
t
FPW4
t
FODF4
244-
244
244+
ns
3
ST_FPo0/1 Output Delay from Falling edge
of ST_FPo0/1 to falling edge of ST_CKo0/1
122-
/2
122+
/2
ns
4
ST_FPo 0/1Output Delay from Falling edge
of ST_CKo0/1 to rising edge of ST_FPo0/1
t
FODR4
122-
/2
122+
/2
ns
5
ST_CKo0/1 Clock Period
t
CP4
t
CH4
t
CL4
244-
244
244+
ns
6
ST_CKo0/1 Clock Pulse Width High
122-
/2
122+
/2
ns
7
ST_CKo0/1 Clock Pulse Width Low
122-
/2
122+
/2
ns
8
ST_CKo0/1 Clock Rise/Fall Time
t
rC4o
, t
C4o
14
ns
LREF0-7
(1.544 MHz)
t
fREF
t
rREF
NREFo
(8 KHz)
t
R8KO15L
t
R8KO15H
t
R8KOP
t
ROD
t
FPW4
t
FODR4
t
FODF4
ST_FPo0/1
ST_CKo0/1
(4.096 MHz)
t
CL4
t
CH4
t
CP4
t
rC4o
t
fC4o
t
LFBOS
Backplane Frame Boundary
Local Output Frame Boundary
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