參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù)： 15/86頁(yè)
文件大?。?/td> 701K
代理商： MT90866AG2
MT90866
Data Sheet
15
Zarlink Semiconductor Inc.
W4, Y3, V4, W3,
Y2, V3, W2, V2,
U3, U2, U1, T3,
T2, T1
A0 - A13
Address 0 - 13 (5 V Tolerant Inputs).
These are the address lines to the
internal memories and registers.
P3, P2, P1, N2,
N3, N1, M1, M2,
M3, L1, L2, L3,
K1, K2, K3, J3
D0 - D15
Data Bus 0 - 15 (5 V Tolerant I/Os)
. These pins form the 16-bit data bus of
the microport.
J1
DTA
Data Transfer Acknowledge (5 V Tolerant Output)
. This active low output
indicates that a data bus transfer is completed. A pull-up resistor is required
to hold a high level.
B9
PCI_OE
PCI Output Enable (3.3 V Tolerant Input)
. This active low input is the
control signal used to tristate the STio0 - 31 pins during hot-swapping.
During normal operation this signal should be low.
W13
C64BYPS
PLL Bypass Clock Input (5 V Tolerant Input).
Used for device testing. In
functional mode, this input MUST be low.
V11
TM1
APLL Test Pin 1 (3.3 V Input).
Use for APLL testing only. In normal
operation, this input should be connected to ground.
Y10
TM2
APLL Test Pin 2 (3.3 V Input).
Use for APLL testing only. In normal
operation, this input should be connected to ground.
W10
SG1
APLL Test Control (3.3 V Input).
Use for APLL testing only. In normal
operation, this input should be connected to ground.
W11
AT1
Analog Test Access (5 V Tolerant I/O).
Use for APLL testing only. No
connection for normal operation.
Y11
DT1
Digital Test Access Output (5 V Tolerant Output).
Use for APLL testing
only. No connection for normal operation.
W5
TMS
Test Mode Select (3.3 V Input with Internal pull-up).
JTAG signal that
controls the state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
W6
TDi
Test Serial Data In (3.3 V Input with Internal pull-up)
. JTAG serial test
instructions and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Y4
TDo
Test Serial Data Out (3.3 V Tolerant Tri-state Output)
. JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
V6
TCK
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test logic.
This pin should be low when JTAG is not enabled.
Y5
TRST
Test Reset (3.3 V Input with Internal pull-up).
Asynchronously initializes
the JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin
should be pulled low to ensure that the MT90866 is in normal functional
mode.
Y6
IC0
Leave unconnected for normal operation.
Pin Description (continued)
PBGA
Ball Number
Name
Description
相關(guān)PDF資料
PDF描述
MT90869 Flexible 16K Digital Switch (F16kDX)
MT90869AG Flexible 16K Digital Switch (F16kDX)
MT90870 Flexible 12 k Digital Switch (F12kDX)
MT90871AV Flexible 8K Digital Switch (F8KDX)
MT90871 Flexible 8K Digital Switch (F8KDX)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90866AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch
MT90868AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays
MT90868AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays
MT90869 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX)
MT90869AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*