參數(shù)資料
型號(hào): MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù): 23/86頁(yè)
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
23
Zarlink Semiconductor Inc.
11.0 Address Mapping of Memories and Registers
The address bus on the microprocessor interface selects the internal registers and memories of the MT90866. If
the address bit A13 is low, then the registers are addressed by A12 to A0 as shown in Table 7 on page 23.
A13 - A0
Location
0000
H
0001
H
0002
H
0003
H
0004
H
0005
H
0006
H
0007
H
0008
H
0009
H
000A
H
000B
H
000C
H
000D
H
000E
H
to 001B
H
001C
H
001D
H
001E
H
001F
H
0020
H
0021
H
0022
H
0023
H
0024
H
to 0026
H
0027
H
0028
H
0029
H
002A
H
002B
H
Table 7 - Address Map For Internal Registers (A13 = 0)
Control Register, CR
Device Mode Selection Register, DMS
Block Programming Mode Register, BPM
Reserved
Local Input Bit Delay Register 0, LIDR0
Local Input Bit Delay Register 0, LIDR1
Local Input Bit Delay Register 2, LIDR2
Local Input Bit Delay Register 3, LIDR3
Local Input Bit Delay Register 4, LIDR4
Local Input Bit Delay Register 5, LIDR5
Local Input Bit Delay Register 6, LIDR6
Local Input Bit Delay Register 7, LIDR7
Local Input Bit Delay Register 8, LIDR8
Local Input Bit Delay Register 9, LIDR9
Reserved
Backplane Output Advancement Register 0, BOAR0
Backplane Output Advancement Register 1, BOAR1
Backplane Output Advancement Register 2, BOAR2
Backplane Output Advancement Register 3, BOAR3
Local Output Advancement Register 0, LOAR0
Local Output Advancement Register 1, LOAR1
Local Output Advancement Register 2, LOAR2
Local Output Advancement Register 3, LOAR3
Reserved
Local BER Input Selection Register, LBIS
Local BER Register, LBERR
Backplane BER Input Selection Register, BBIS
Backplane BER Register, BBERR
DPLL Operation Mode Register 1, DOM1
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