參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù)： 60/86頁(yè)
文件大?。?/td> 701K
代理商： MT90866AG2
MT90866
Data Sheet
60
Zarlink Semiconductor Inc.
Bit
Primary Master
Mode
Secondary Master Mode
Slave Mode
D
r
BEN (bit 14)
0
- Monitor “B Clocks”
1
- Drive “B Clocks”
0
- Monitor “B Clocks”
AEN (bit 13)
1
- Drive “A Clocks”
0
- Monitor “A Clocks”
0
- Monitor “A Clocks”
RPS (bit 12)
0
- Preferred reference is
PRI_REF
0
- Preferred reference is
PRI_REF
0
- Preferred reference is
PRI_REF
FS1-0
(bits 11-10)
Frequency of the
secondary
reference
00
- 8 kHz
01
- 1.544 MHz
10
- 2.048 MHz
00
- 8 kHz
01
- 1.544 MHz
10
- 2.048 MHz
11
- 8.192 MHz Clock
(“B Clocks”)
FP1-0
(bits 9-8)
Frequency of the
primary
reference
00
- 8 kHz
01
- 1.544 MHz
10
- 2.048 MHz
11
- 8.192MHz Clock
(“A Clocks”)
11
- 8.192 MHz Clock
(“A Clocks”)
SS3-0
(bits 7-4)
Secondary
reference
selection:
0000
- CTREF1
0001
- CTREF2
1000
- LREF0
1001
- LREF1
1010
- LREF2
1011
- LREF3
1100
- LREF4
1101
- LREF5
1110
- LREF6
1111
- LREF7
0000
- CTREF1
0001
- CTREF2
1000
- LREF0
1001
- LREF1
1010
- LREF2
1011
- LREF3
1100
- LREF4
1101
- LREF5
1110
- LREF6
1111
- LREF7
XXXX
- C8_B_io
When bits
FS1-0
are set to
11
,
C8_B_io is always used as the
secondary reference,
regardless of the values of bits
SS3-0. Output frame pulses
are aligned to FRAME_B_io if
secondary reference is the
active reference
SP3-0
(bits 3-0)
Primary
reference
selection:
0000
- CTREF1
0001
- CTREF2
1000
- LREF0
1001
- LREF1
1010
- LREF2
1011
- LREF3
1100
- LREF4
1101
- LREF5
1110
- LREF6
1111
- LREF7
XXXX
- C8_A_io
When bits
FP1-0
are set to
11
,
C8_A_io is always used as the
primary reference, regardless
of the values of bits SP3-0.
Output frame pulses are
aligned to FRAME_A_io if
primary reference is the active
reference
XXXX
- C8_A_io
When bits
FP1-0
are set to
11
,
C8_A_io is always used as the
primary reference, regardless
of the values of bits SP3-0.
Output frame pulses are
aligned to FRAME_A_io if
primary reference is the active
reference
D
R
MRST (bit 10)
0
- MTIE functional
1
- MTIE reset
0
- MTIE functional
1
- MTIE reset
1
- MTIE MUST be kept in the
reset state in Slave mode
FDM1, FDM0
(bits 9-8)
Failure detect
mode selection
00
- Autodetect Mode
00
- Autodetect Mode
01
- External Mode
(Note 1)
00
- Autodetect Mode
01
- External Mode
(Note 1)
* Note 1: It is assumed that the switching among references is done by an external software control, if the External Mode is
selected.
Table 22 - MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers
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