參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 49/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
49
Zarlink Semiconductor Inc.
5-3
LBPD2-0
Local Block Programming Data Bits:
These bits carry the value to be loaded into the
local connection memory low whenever the Memory Block Programming feature is
activated. After the MBP bit in the control register is set to high and the BPE is set to high,
the contents of the bits LBPD2 - 0 are loaded into bits 15 - 13 of the local connection
memory low. Bits 12 - 0 of the local connection memory low and bits 15 - 0 of the local
connection memory high are programmed to be zero.
2
BPE
Block Programming Enable:
A low to high transition of this bit enables the Memory Block
Programming function. The BPE, BBPD2-0 and LBPD2-0 in the BPM register have to be
defined in the same write operation. Once the BPE bit is set to high, MT90866 requires two
frames to complete the block programming. After the block programming has finished, the
BPE bit returns to low to indicate that the operation is complete. When BPE is high, BPE or
MBP can be set to low to abort the programming operation. When BPE is high, the other
bits in the BPM register must not be changed for two frames to ensure proper operation.
Whenever the microprocessor writes BPE to be high to start the block programming
function, the user must maintain the same logical value on the other bits in the BPM register
to avoid any change in the setting of the device.
1-0
Unused
Reserved.
In functional mode, these bits MUST be low.
Bit
Name
Description
Table 11 - Block Programming Mode (BPM) Register Bits (continued)
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參數(shù)描述
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